similar to: [LLVMdev] How to analyze where the address comes from?

Hi, I am an out-of-tree user of llvm. I am running into an regression issue against llvm 5.0. The issue was introduced by "[BasicAA] Use MayAlias instead of PartialAlias for fallback."( https://reviews.llvm.org/D34318) I have attached a very simple program to reproduce the issue. The symptom is alias analysis report NoAlias to GVN which cause GVN do wrong optimization. The BasicAA

> -----Original Message----- > From: meinersbur at googlemail.com [mailto:meinersbur at googlemail.com] On > Behalf Of Michael Kruse > Sent: Tuesday, October 17, 2017 3:26 PM > To: Song, Ruiling <ruiling.song at intel.com> > Cc: llvm at meinersbur.de; llvm-dev at lists.llvm.org > Subject: Re: Possible bug of Alias Analysis? > > 2017-10-17 8:45 GMT+02:00 Song,

> -----Original Message----- > From: meinersbur at googlemail.com [mailto:meinersbur at googlemail.com] On > Behalf Of Michael Kruse > Sent: Wednesday, October 18, 2017 1:18 PM > To: Song, Ruiling <ruiling.song at intel.com> > Cc: Michael Kruse <llvm at meinersbur.de>; llvm-dev at lists.llvm.org > Subject: Re: Possible bug of Alias Analysis? > > 2017-10-18

> On Dec 21, 2016, at 10:26, Ruiling Song <ruiling.song83 at gmail.com> wrote: > > > > 2016-12-20 22:14 GMT+08:00 Tom Stellard <tom at stellard.net <mailto:tom at stellard.net>>: > > > > On Tue, Dec 20, 2016 at 11:00:09AM +0800, Ruiling Song wrote: > > > Hi, > > > > > > I am working on a new LLVM target for Intel GPU, which

On Wed, Dec 21, 2016 at 10:31:57AM -0500, Matt Arsenault wrote: > > > On Dec 21, 2016, at 10:26, Ruiling Song <ruiling.song83 at gmail.com> wrote: > > > > > > > > 2016-12-20 22:14 GMT+08:00 Tom Stellard <tom at stellard.net <mailto:tom at stellard.net>>: > > > > > > On Tue, Dec 20, 2016 at 11:00:09AM +0800, Ruiling Song

2016-12-20 22:14 GMT+08:00 Tom Stellard <tom at stellard.net>: > > On Tue, Dec 20, 2016 at 11:00:09AM +0800, Ruiling Song wrote: > > Hi, > > > > I am working on a new LLVM target for Intel GPU, which also has same kind > > of scalar/vector register classes used in AMDGPU target. Like for a i32 > > virtual register, it will be held in scalar register if its

Hi, I am currently working on an opencl project based on LLVM, the target device is 32bit. I met a problem that some llvm passes like GVN SROA will generate some IR operating on wide integer types like i128 or i512. But the device does not support such kind of data type. Is there any idea on how to lower this kind of IR to only operate on i32 or vector of i32? Or is there any existing code handle

Hi, The gpu target I am working on requires the 'value' and 'address' operands of memory store instruction in consecutive register. Anybody has suggestion? - Ruiling -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160909/e9d330bc/attachment.html>

Is it just an optimization pass? Maybe I can cancel it somehow with a flag or by doing some code editing? Can you point me to which passes may do that? I'm working on editing a backend that can't work with anything larger than 32 bits. Does the legalize stage work on IR code? Maybe i can use that? On Jan 29, 2015 5:41 AM, Ruiling Song <ruiling.song83 at gmail.com> wrote: LLVM

On Tue, Dec 20, 2016 at 11:00:09AM +0800, Ruiling Song wrote: > Hi, > > I am working on a new LLVM target for Intel GPU, which also has same kind > of scalar/vector register classes used in AMDGPU target. Like for a i32 > virtual register, it will be held in scalar register if its value is > uniform across a wavefront/warp, otherwise it will be in a vector register. > Does

Hi Escha, Great to have your comment! Do you have any specific reason for not doing like this? I am not sure whether I understand your point correctly. For "just model one thread", do you mean "only considering ONE of the 8/16 working lanes that running in lock-step way"?? For my case, may be something like I only need to define r0~r127 as register for i32 register (each r#

Some code in GVN.cpp: static Value *CoerceAvailableValueToLoadType(Value *StoredVal, Type *LoadedTy, Instruction *InsertPt, const DataLayout &DL) { .... // Convert vectors and fp to integer, which can be manipulated. if (!StoredValTy->isIntegerTy()) {

Generally legalize at IR level is not a good idea. But if you need legalization on IR code, you can check PNaCl project. https://chromium.googlesource.com/native_client/pnacl-llvm/ The pass is located at: lib/Transforms/NaCl/ExpandLargeIntegers.cpp You need make some change, as the pass split large integer into 64bit integers. 2015-01-29 16:06 GMT+08:00 Alon Shaltiel (ashaltie) <ashaltie at

> On Sep 13, 2017, at 9:03 PM, jin chuan see via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi All, > > Thanks for the reply. I managed to identify and fixed a few errors in my implementation. > > However, there are a few errors that i am not sure what is it indicating. > For starters, i think i should explain what i am trying to achieve. > > I am

Hello Everyone, I am trying to make a new LLVM backend target for Intel GPU. I would start from targeting OpenCL language first. But I am not quite familiar with LLVM backend infrastructure. I have some problem on describing the RegisterInfo. Intel GPU launches lots of hardware threads to do GPGPU workload. Each hardware thread has 128 registers(r0-r127), with each one of size 32 byte. Each

Hi, I am working on a new LLVM target for Intel GPU, which also has same kind of scalar/vector register classes used in AMDGPU target. Like for a i32 virtual register, it will be held in scalar register if its value is uniform across a wavefront/warp, otherwise it will be in a vector register. Does AMDGPU already done this? I read the code, but I didn't figure out how to do this. Anybody has

Running llc with '-verify-machineinstrs' may tell you which instruction break the SSA form. Ruiling From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of jin chuan see via llvm-dev Sent: Monday, September 11, 2017 10:02 AM To: Matthias Braun <mbraun at apple.com> Cc: llvm-dev at lists.llvm.org Subject: Re: [llvm-dev] Live Register Spilling Sorry about the

Yes, the arch is just as you said, something like AMD GPU, but Intel GPU don't have separate register file for 'scalar/vector'. In fact my idea of defining the register tuples was borrowed from SIRegisterInfo.td in AMD GPU. But seems that AMD GPU mainly support i32/i64 register type, while Intel GPU also support byte/short register type. So I have to start defining the registers from

Hi, The ISA I am working on is always encoded in 128bit binary format. I find that getBinaryCodeForInst() only return at most 64bit Encoding. So, I think the proper way to encode the instructions is to write the XXXMCCodeEmitter by myself instead of automatic generation. right? Is there any guideline/suggestion on how to write the XXXMCCodeEmitter using current LLVM infrastructure? I want to use

Hi, everyone I need to create a 429497 x 429497 matrix. When I use *matrix(0,429497,429497)* I got the error information : Error in matrix(0, 429497, 429497) : too many elements specified Then I use "ff" package, try to store this matrix on disk * x<-ff(0,dim=c(429497,429497)* And I got the error information : Error in if (length < 0 || length > .Machine$integer.max)