similar to: [LLVMdev] questions about memory dependence analysis

Hi, I want to use memory dependence analysis in my pass, but I feel the default alias analysis is not precise enough. How could I choose to use another alias analysis algorithm? I have tried opt -load mypass.so -basicaa xx.bc > /dev/null. But I feel the alias analysis algorithm does not change. Do I need to add something in my codes? Thanks a lot! Best,

----- Original Message ----- > From: "Jingyue Wu" <jingyue at google.com> > To: "songlh" <songlh at cs.wisc.edu>, llvmdev at cs.uiuc.edu > Sent: Wednesday, October 15, 2014 2:50:12 PM > Subject: Re: [LLVMdev] how to choose which alias analysis used in my pass? > > > Isn't -basicaa the default alias analysis already? No, -basicaa is added

hi, I have few question about breaking anti-dependence of postRAScheduler in LLVM. when I use command line "clang -target arm -mcpu=cortex-a8 -O2 -integrated-as -c test.c -o test.o" and get objdump file as follows: ldrr1, [r0,#16]----(1 str r1, [r0,#32]----(2 ldr r1, [r0,#12]----(3 str r1, [r0,#36]----(4 ldr r1, [r0,#08]----(5 str r1, [r0,#40]----(6 However, I expect that instruction

----- Original Message ----- > > > > hi, > I have few question about breaking anti-dependence of postRAScheduler > in LLVM. > when I use command line "clang -target arm -mcpu=cortex-a8 -O2 > -integrated-as -c test.c -o test.o" > and get objdump file as follows: > ldr r1, [r0,#16]----(1 > str r1, [r0,#32]----(2 > ldr r1, [r0,#12]----(3 > str r1,

Hi All, If the target supports quad-register R0:R1:R2:R3 (Rn is 32-bit register), is it possible mapping quad-register to v4i32 so that the following example work? typedef int v4si __attribute__ ((vector_size (16))); void foo(v4si i) { v4si j = i; } I don't know how to write CallingConv.td to represent the concept of occupying quad-register R0:R1:R2:R3 once seeing

> On 1/26/11 3:00 PM, songlh at cs.wisc.edu wrote: >>> On 1/26/11 2:40 PM, songlh at cs.wisc.edu wrote: >>>> thanks! >>>> >>>> After I check the ll file, I find this: >>>> >>>> %1 = load %struct.nsAString** %aBuf_addr, align 4, !dbg !2048 >>>> %2 = getelementptr inbounds %struct.nsAString* %1, i32 0, i32 0, !dbg

> On 1/26/11 2:40 PM, songlh at cs.wisc.edu wrote: >> thanks! >> >> After I check the ll file, I find this: >> >> %1 = load %struct.nsAString** %aBuf_addr, align 4, !dbg !2048 >> %2 = getelementptr inbounds %struct.nsAString* %1, i32 0, i32 0, !dbg >> !2048 >> %3 = getelementptr inbounds %struct.nsISupports* %2, i32 0, i32 0, !dbg >> !2048

On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote: > The code below in lib/Target/ARM/ARMRegisterInfo.td is where you > should look into, > > // Integer registers > def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>; > def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>; > > ... That's the easy part. ARM (AArch32) has 16 registers

On 1/26/11 3:00 PM, songlh at cs.wisc.edu wrote: >> On 1/26/11 2:40 PM, songlh at cs.wisc.edu wrote: >>> thanks! >>> >>> After I check the ll file, I find this: >>> >>> %1 = load %struct.nsAString** %aBuf_addr, align 4, !dbg !2048 >>> %2 = getelementptr inbounds %struct.nsAString* %1, i32 0, i32 0, !dbg >>> !2048 >>> %3

Hello. Could you please tell me how can I optimize with the back end (llc) the following piece of assembly code generated by llc: // NOTE: my processor accepts loops in the form of REPEAT(num_times)..END_REPEAT R0 = ... REPEAT(256) R5 = R0; // basically unnecessary reg. copy REPEAT(256) R10 = LS[R4]; R2 = LS[R5]; R4 =

Lately I have had a few discussions of what it means for a register to be unallocatable or reserved. As this comes up every now and again and I often struggled answering such questions I decided to write down some definite rules and codify the current usage and assumptions. I plan to put the rules below into the doxygen comments of MachineRegisterInfo etc. And I also hope that people will correct

As Adrian said, we'd need to see the source of foo() to assess what the location-list for bar ought to be. Without actually going to look, I would guess that 'poplt' is considered a conditional move, therefore r4's contents are not guaranteed after it executes (i.e. it is a clobber). If one operand of 'poplt' is 'pc' then of course it is also a conditional indirect

> On 1/26/11 3:06 PM, songlh at cs.wisc.edu wrote: >>> [snip] >>> -- John T. >> Sorry, I am asking the second question. >> " >> how to determine, within an LLVM pass, what the >> possible target(s) of an indirect function call might be? > > There are at least two solutions. > > The first is to use the CallGraph analysis pass. It

Thanks a lot! I finally fix my problem. My code is like this: //CallInst* pCall pCall is a printf called in my situation if( ConstantExpr * pCE = dyn_cast<ConstantExpr>( pCall->getArgOperand(0))){ if( GlobalVariable * pGV = dyn_cast<GlobalVariable>( pCE->getOperand(0))){ if( ConstantArray * pCA = dyn_cast<ConstantArray>(

Hi, all On the website, it says, CCAssignToRegWithShadow <registerList, shadowList> — similar to CCAssignToReg, but with a shadow list of registers I don't know when we should use CCAssignToRegWithShadow. Because I am not a architecture expert, please bear with my naive question. Take ARMCallingConv.td as an example, CCIfType<[i32], CCIfAlign<"8",

Hi, I just notice that front-end will add an extra block for switch instruction without default. How could I identify basic blocks added due to this reason? The added codes looks like: sw.default.i625: ; preds = %if.end512 tail call void @fancy_abort(i8* getelementptr inbounds ([38 x i8]* @.str, i64 0, i64 0), i32 3045, i8* getelementptr inbounds

Hi, I'm trying to write an LLVM backend for Epiphany arch, and I wonder if someone can give me some advice on how to implement load/store optimization. The CPU itself is 32-bit, but it supports wider 64-bit loads and store. So the basic idea is to make use of those by combining narrow ones. I've checked how it is done in AArch64 and Hexagon, and my current code is very close to the

Hello, Has anyone taken a look at this bug? I really want to fix this, but as Paul pointed out, this requires a lot of care... Thank you for your help Son Tuan Vu On Fri, Apr 27, 2018 at 7:29 PM, Son Tuan VU <sontuan.vu119 at gmail.com> wrote: > Thank you all for taking a look at this. I pasted the C source then > deleted it because I was afraid that it was too long to read...

Hi, I want to increase the number of integer registers in the ARM machine. I don't have any idea how/where I can start. Can anybody help me? By the way, what are the following line in the ARMRegisterInfo.td specify: def qsub_0 def qsub_1 .... Thanks Best Regards, A. Yazdanbakhsh

Hi all, Consider this ARM assembly code of a C function: 00008124 <foo>: 8124: push {r4, r6, r7, lr} 8126: add r7, sp, #8 8128: mov r4, r0 812a: ldrsb.w r0, [r2] 812e: cmp r0, #1 8130: itt lt 8132: movlt r0, #85 ;