Displaying 20 results from an estimated 200 matches similar to: "[LLVMdev] How to deal with wider Integer type?"
2014 Sep 04
2
[LLVMdev] How to deal with wider Integer type?
Some code in GVN.cpp:
static Value *CoerceAvailableValueToLoadType(Value *StoredVal,
Type *LoadedTy,
Instruction *InsertPt,
const DataLayout &DL) {
....
// Convert vectors and fp to integer, which can be manipulated.
if (!StoredValTy->isIntegerTy()) {
2015 Jan 29
2
[LLVMdev] prevent frontend from emitting i64
Is it just an optimization pass? Maybe I can cancel it somehow with a flag or by doing some code editing? Can you point me to which passes may do that?
I'm working on editing a backend that can't work with anything larger than 32 bits. Does the legalize stage work on IR code? Maybe i can use that?
On Jan 29, 2015 5:41 AM, Ruiling Song <ruiling.song83 at gmail.com> wrote:
LLVM
2016 Dec 21
0
Assign different RegClasses to a virtual register based on 'uniform' attribute?
> On Dec 21, 2016, at 10:26, Ruiling Song <ruiling.song83 at gmail.com> wrote:
>
>
>
> 2016-12-20 22:14 GMT+08:00 Tom Stellard <tom at stellard.net <mailto:tom at stellard.net>>:
> >
> > On Tue, Dec 20, 2016 at 11:00:09AM +0800, Ruiling Song wrote:
> > > Hi,
> > >
> > > I am working on a new LLVM target for Intel GPU, which
2015 Jan 30
0
[LLVMdev] prevent frontend from emitting i64
Generally legalize at IR level is not a good idea.
But if you need legalization on IR code, you can check PNaCl project.
https://chromium.googlesource.com/native_client/pnacl-llvm/
The pass is located at: lib/Transforms/NaCl/ExpandLargeIntegers.cpp
You need make some change, as the pass split large integer into 64bit
integers.
2015-01-29 16:06 GMT+08:00 Alon Shaltiel (ashaltie) <ashaltie at
2016 Dec 21
1
Assign different RegClasses to a virtual register based on 'uniform' attribute?
On Wed, Dec 21, 2016 at 10:31:57AM -0500, Matt Arsenault wrote:
>
> > On Dec 21, 2016, at 10:26, Ruiling Song <ruiling.song83 at gmail.com> wrote:
> >
> >
> >
> > 2016-12-20 22:14 GMT+08:00 Tom Stellard <tom at stellard.net <mailto:tom at stellard.net>>:
> > >
> > > On Tue, Dec 20, 2016 at 11:00:09AM +0800, Ruiling Song
2016 Dec 21
3
Assign different RegClasses to a virtual register based on 'uniform' attribute?
2016-12-20 22:14 GMT+08:00 Tom Stellard <tom at stellard.net>:
>
> On Tue, Dec 20, 2016 at 11:00:09AM +0800, Ruiling Song wrote:
> > Hi,
> >
> > I am working on a new LLVM target for Intel GPU, which also has same
kind
> > of scalar/vector register classes used in AMDGPU target. Like for a i32
> > virtual register, it will be held in scalar register if its
2016 Aug 23
2
How to describe the RegisterInfo?
Hi Escha,
Great to have your comment! Do you have any specific reason for not doing
like this?
I am not sure whether I understand your point correctly. For "just model
one thread",
do you mean "only considering ONE of the 8/16 working lanes that running in
lock-step way"??
For my case, may be something like I only need to define r0~r127 as
register for i32 register (each r#
2014 Nov 19
4
[LLVMdev] How to analyze where the address comes from?
Hi,
I want to get the information where the address of load/store comes from,
like below load instruction, %152 may come from a getelementpr, or comes
from some gep+ptrtoint+add+inttoptr... instructions. what's the recommended
way to find the original memory pointer?
%153 = load <2 x i16> addrspace(1)* %152, align 2
going through the use-def chain seems not easy, because the
2015 Mar 20
3
[LLVMdev] Mul & div support for wider-than-legal types
Hi LLVM,
1. Can mul and/or div support be added for big integer types like i256?
2. What are the limits?
3. If yes, how should it be done?
I have experience only with X86 target and know that mul i128 works and div
i128 is lowered to function call from compile-rt like library (what works
only if you link with such library). Can that support be extended?
- Paweł
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2017 Oct 18
2
Possible bug of Alias Analysis?
> -----Original Message-----
> From: meinersbur at googlemail.com [mailto:meinersbur at googlemail.com] On
> Behalf Of Michael Kruse
> Sent: Wednesday, October 18, 2017 1:18 PM
> To: Song, Ruiling <ruiling.song at intel.com>
> Cc: Michael Kruse <llvm at meinersbur.de>; llvm-dev at lists.llvm.org
> Subject: Re: Possible bug of Alias Analysis?
>
> 2017-10-18
2017 Oct 18
2
Possible bug of Alias Analysis?
> -----Original Message-----
> From: meinersbur at googlemail.com [mailto:meinersbur at googlemail.com] On
> Behalf Of Michael Kruse
> Sent: Tuesday, October 17, 2017 3:26 PM
> To: Song, Ruiling <ruiling.song at intel.com>
> Cc: llvm at meinersbur.de; llvm-dev at lists.llvm.org
> Subject: Re: Possible bug of Alias Analysis?
>
> 2017-10-17 8:45 GMT+02:00 Song,
2017 Oct 17
3
Possible bug of Alias Analysis?
Hi,
I am an out-of-tree user of llvm. I am running into an regression issue against llvm 5.0.
The issue was introduced by "[BasicAA] Use MayAlias instead of PartialAlias for fallback."( https://reviews.llvm.org/D34318)
I have attached a very simple program to reproduce the issue. The symptom is alias analysis report NoAlias to GVN which cause GVN do wrong optimization.
The BasicAA
2016 Sep 09
3
how to allocate consecutive register?
Hi,
The gpu target I am working on requires the 'value' and 'address' operands
of memory store instruction in consecutive register. Anybody has suggestion?
- Ruiling
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2016 Dec 20
0
Assign different RegClasses to a virtual register based on 'uniform' attribute?
On Tue, Dec 20, 2016 at 11:00:09AM +0800, Ruiling Song wrote:
> Hi,
>
> I am working on a new LLVM target for Intel GPU, which also has same kind
> of scalar/vector register classes used in AMDGPU target. Like for a i32
> virtual register, it will be held in scalar register if its value is
> uniform across a wavefront/warp, otherwise it will be in a vector register.
> Does
2016 Aug 23
2
How to describe the RegisterInfo?
Yes, the arch is just as you said, something like AMD GPU, but Intel GPU
don't have separate register file for 'scalar/vector'.
In fact my idea of defining the register tuples was borrowed from
SIRegisterInfo.td in AMD GPU.
But seems that AMD GPU mainly support i32/i64 register type, while Intel
GPU also support byte/short register type.
So I have to start defining the registers from
2013 Jan 02
2
[LLVMdev] [DragonEgg] [Polly] Should we expect DragonEgg to produce identical LLVM IR for identical GIMPLE?
On 01/01/2013 02:45 PM, Duncan Sands wrote:
> Hi Dmitry,
>
>>
>> In our compiler we use a modified version LLVM Polly, which is very
>> sensitive to
>> proper code generation. Among the number of limitations, the loop region
>> (enclosed by phi node on induction variable and branch) is required to
>> be free
>> of additional memory-dependent
2017 Sep 14
2
Live Register Spilling
> On Sep 13, 2017, at 9:03 PM, jin chuan see via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
> Hi All,
>
> Thanks for the reply. I managed to identify and fixed a few errors in my implementation.
>
> However, there are a few errors that i am not sure what is it indicating.
> For starters, i think i should explain what i am trying to achieve.
>
> I am
2015 Feb 02
3
[LLVMdev] LLVM IR i128
Hi everyone!
Here, I have a question and am curious about i128. I want to know how the LLVM handle i128, because many compiler backend doesn't support i128 directly. So I am very curious and want to how the llvm handle this situation? Besides i128, such as i256, i512, even i24? Thanks.
Best Regards
Wu Zhao
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2014 Jan 08
3
[LLVMdev] reference to non-static member function must be called
Hi,everyone.
I'm writing a pass in which a CallInst to an external function will be
inserted. The function is declared like this:
void func(int a, unsigned chat *p);
and in the Pass(a Function Pass ,and using the InstVistor template ), I
wrote like this:
void visitStoreInst(StoreInst &SI)
{
//Get the refference of the types
Module *M =
2013 Jan 02
0
[LLVMdev] [DragonEgg] [Polly] Should we expect DragonEgg to produce identical LLVM IR for identical GIMPLE?
Hi Duncan & Tobi,
Thanks a lot for your interest, and for pointing out differences in GIMPLE
I missed.
Attached is simplified test case. Is it good?
Tobi, regarding runtime alias analysis: in KernelGen we already do it along
with runtime values substitution. For example:
<------------------ __kernelgen_main_loop_17: compile started
--------------------->
Integer args substituted: