similar to: [LLVMdev] FPU cannot be compatible with -soft-float code on mips by llc

Hi Andrea    Thank you your replying.    I do like your letter. Add following to line to MipsISelLowering.cpp. As your words,   @llvm.convert.to.fp16  can compile successfully. However, the runtime is not right. +  setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);+  setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand); Robin yalong at multicorewareinc.com  From: Andrea Di

For the following C code __fp16 x, y, z, w; void foo() { x = y + z; x = x + w; } clang produces IR that extends each operand to float and then truncates to half before assigning to x. Like this define dso_local void @foo() #0 !dbg !18 { %1 = load half, half* @y, align 2, !dbg !21 %2 = fpext half %1 to float, !dbg !21 %3 = load half, half* @z, align 2, !dbg !22 %4 = fpext half %3 to float, !dbg

Thanks Eli. I forgot to bring up the strict FP questions which I was working on when I found this. If we're in a strict FP function, do the fp_to_f16/f16_to_fp emitted by promoting load/store/bitcast need to be strict versions of fp_to_f16/f16_to_fp. And if so where do we get the chain, especially for the bitcast case which isn't a chained node. ~Craig On Tue, Dec 10, 2019 at 3:18 PM

On 07/09/2014 12:41 PM, Matt Arsenault wrote: > On 07/09/2014 03:30 PM, yalong at multicorewareinc.com wrote: >> Thank you Kevin!!! >> If I use fptrunc and bitcast realise NEON vcvtt ( I can sure, >> "fptrunc double %tmp to float" is right, but "fptrunc float %tmp to >> half" is wrong). My target platform is MIPS. The command as following:

_______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Hi guys, The PV ABI of xen will clear CR0.TS before trapping into the PV guest kernel's exception handler, so the exception handler in guest kernel runs with CR0.TS clear at the very beginning (which is different with on baremetal). In Xenolinux and mainline Linux kernel before 2.6.26 everything is fine since they don't sleep nor enable interrupts during the handler, however the current

Hi guys, The PV ABI of xen will clear CR0.TS before trapping into the PV guest kernel's exception handler, so the exception handler in guest kernel runs with CR0.TS clear at the very beginning (which is different with on baremetal). In Xenolinux and mainline Linux kernel before 2.6.26 everything is fine since they don't sleep nor enable interrupts during the handler, however the current

This patch enables LWP related CPUID to HVM guests. Signed-off-by: Wei Huang <wei.huang2@amd.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

More specifically, about this patch: http://git.xiph.org/?p=flac.git;a=commitdiff;h=70b078cfd5f9d4b0692c33f018cac3c652b14f90 I downloaded the latest code from git (flac-70b078c), disabled all SSE optimizations in the code and compiled it (GCC 4.8.2). This patch doesn't change FLAC output. Either gcc is too smart and optimizes this new code back to the old, or this fix is MSVS-specific. Or

Olivier Tristan <o.tristan at uvi.net> ?????(?) ? ????? ?????? Fri, 21 Mar 2014 22:41:00 +0400: > Check with -mfpmath=387 to be sure that x87 FPU code is used and not some > SSE optim made by GCC I added "XIPH_ADD_CFLAGS([-mfpmath=387])" into configure.ac Still the result is different from SSE version. --------------- MSVS adds two instructions to the generated code after

Hi, i was asking in the irc about any developer or group of devs who could enable a vorbis encoder to run on a MIPS32 architecture. There is a payment for whoever can make this happen. The main motivation comes from an art project (so is the funding) All credits will go to whoever is able to improve the code and makes the port as a package .ipk for the openwrt firmwares (preferably kamikaze).

Dear developers, is there (already) a platform-independent way for (temporarily!) changing the fpu control word? More precisely: I am looking for functions (accessible from C code in R packages) which read and write the fpu control word on x86 cpus (and cause no harm otherwise), because I need to (temporarily) turn off internal 80-bit precision for some algorithms relying on 64-bit IEEE

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 ============================================================================= FreeBSD-SA-06:14.fpu Security Advisory The FreeBSD Project Topic: FPU information disclosure Category: core Module: sys Announced: 2006-04-19

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 ============================================================================= FreeBSD-SA-06:14.fpu Security Advisory The FreeBSD Project Topic: FPU information disclosure Category: core Module: sys Announced: 2006-04-19

I started a brand new session in R 2.10.1 (on Windows). If it matters, I am running the community edition of MySQL 5.0.67, and it is all running fine. I am just beginning to examine the process of getting timer series data from one table in MySQL, computing moving averages and computing a selection of estimates based on relations among moving averages of different variates, and storing all the

Hi, all: I am trying to test half float point support in llvm, I found clang can generate bitcode for __fp16, while llc can't generate code for it, the error message is like this LLVM ERROR: Cannot select: 0x26a68e0: i16 = fp32_to_fp16 0x26a67d8 [ORD=2] [ID=4] 0x26a67d8: f32,ch = CopyFromReg 0x2693060, 0x26a66d0 [ORD=2] [ID=3] 0x26a66d0: f32 = Register %vreg1 [ID=1] In function: test

Hey everybody, I am struggling to get rid of a problem which seems to be related to a multi-return value optimization: I generate bitcode for a c++-function with llvm-g++ which is then linked, transformed and optimized at runtime using LLVM. The function has quite a few parameters, including structs and struct-pointers with 3 float fields. The problem is, that I require the function to preserve

Hi Ralf, > llvm-gcc -c -emit-llvm -O3 produces this: > > %struct.float3 = type { float, float, float } > define void @test(double %a.0, float %a.1, %struct.float3* nocapture > %res) nounwind noinline { > entry: > %tmp8 = bitcast double %a.0 to i64 ; <i64> [#uses=1] > %tmp9 = zext i64 %tmp8 to i96 ; <i96> [#uses=1] >

Hey everybody, I am struggling to get rid of a problem which seems to be related to a multi-return value optimization: I generate bitcode for a c++-function with llvm-g++ which is then linked, transformed and optimized at runtime using LLVM. The function has quite a few parameters, including structs and struct-pointers with 3 float fields. The problem is, that I require the function to preserve

Hey Duncan, hey everybody else, I just stumbled upon a problem in the latest llvm-gcc trunk which is related to my previous problem with the 64bit ABI and structs: Given the following code: struct float3 { float x, y, z; }; extern "C" void __attribute__((noinline)) test(float3 a, float3* res) { res->y = a.y; } int main(void) { float3 a; float3 res; test(a,