similar to: [LLVMdev] How to resolve decoding conflict?

Hello, I'm implementing a port of LLVM for PowerPC VLE. It's a compressed instruction set similar to mips16 and ARM Thumb. Instruction encoding (VLE/non-vle) is selected for a given memory region by an attribute in a memory area descriptor. Targets supporting this that I know of are all bare-metal (so powerpc-none-elf). I'm trying to implement ELF support right now. VLE ELF files

Dear List: I'm working to construct a very large sparse matrix and have found relief using the SparseM package. I have encountered an issue that is confusing to me and wonder if anyone may be able to suggest a smarter solution. The matrix I'm creating is a covariance matrix for a larger research problem that is subsequently used in a simulation. Below is the latex form of the matrix if

Hi We have a mission critical Dell rackmount server. I tried to reboot it via an ssh session and it just kept running! The command I used was: [root at vle tmp]# shutdown -r now Broadcast message from root (pts/0) (Tue Oct 10 08:28:44 2006): The system is going down for reboot NOW! Looking at /var/log/messages it says: Oct 10 08:28:44 vle shutdown: shutting down for system reboot But

Hi List. We have an Redhat 8.0 machine who acts as an printserver. I'm sharing printers via Samba and using CUPS. Samba is 2.2.7a and CUPS 1.1.8. The Microsoft clients (Win9x, Win NT, Win 2k) is downloading the driver from the server. I had no problem to install and upload up to 55 printers but now I am not able to set the driver. I can install more printers, but when cupsaddsmb is running

I'm currently trying to get llvm-mc --disassemble working for the XCore backend. Up until recently there was no instruction encoding / decoding information on any of the XCore instructions so Im incrementally adding this information at the same time as adding tests for the disassembler. However I've run into a problem and I'm not sure of the best way to solve it. With some of the

I've been working on adding support for a (semi-proprietary) extension for PowerPC called "Paired-Singles". It's a SIMD instruction set supporting various operations on a vector of 2 32-bit floating point numbers. The Extension is found in the PowerPC 750CL, modified variants of it are used in the Nintendo GameCube (Gekko), the Nintendo Wii (Broadway) and the Nintendo Wii U

Hello Daniel, At the moment we are preparing the patch for disassembling microMIPS 16 bit instructions and it will be on Phabricator tomorrow or on Wednesday. Functionality is implemented in MipsDisassembler::getInstruction where first two bytes are read and decodeInstruction is called with DecoderTableMicroMips16 and only if it fails we read 4 bytes and call decodeInstruction with

Owen, As I recall, we had some similar issues with custom decoders needing to cooperate on ARM. Do you remember the details? -Jim On Dec 18, 2012, at 2:37 AM, Richard Osborne <richard at xmos.com> wrote: > I'm currently trying to get llvm-mc --disassemble working for the XCore backend. Up until recently there was no instruction encoding / decoding information on any of the XCore

Hi, I'd like to propose extending the supported syntax for AssemblerPredicates to allow sets of SubtargetFeatures to be listed, but where only one in the list has to be enabled for the predicate to be true. The condition string which forms a AssemblerPredicate already allows multiple features to be defined, separated by commas, and this means all of these features must be present. For

Hi, We have this line in micromips-16-bit-instructions.s # CHECK-EB: addu16 $6, $17, $4 # encoding: [0x07,0x42] However, when I check this with llvm-mc, like below, I dont get back the assembly. This is against the latest LLVM code. What is wrong here? Thanks, Jun $ echo "0x07,0x42"|./Release+Asserts/bin/llvm-mc -disassemble -triple=mips -show-encoding -mattr=micromips

Newbie question (just joined the list) Is anyone running Ruby on Rails in a teaching environment? Regards John John Colby BA, MBCS, PGCertE Lecturer, Department of Computing, The Business School Room F316, Galton Building, University of Central England, Franchise Street, Perry Barr, Birmingham B42 2SU Tel: +44 (0) 121 331 6937, Fax +44 (0) 121 331 6281, Mobile: 07795 215 912

Hello everyone, This is not directly related to CentOS but still: we are trying to set up some storage servers to run under Linux - most likely CentOS. The storage volume would be in the range specified: 8-15 TB. Any recommendations as far as hardware? Thanks. Boris. -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi, Even i have installed en running samba on my pc the utility rpcclient is not available. If i am correct i need this for connecting drivers to printers, or a couple of printers to one specific driver. You are reffering to a couple of SAMBA books, but can i find information in these books what is not available in HOW-TO's or documents at your site. Thanks. (i'am a beginner in

Hi all, I found that there will be a memory leak if asterisk running day by day without restart. Is it good to restart asterisk service daily? What is the better way to restart it daily like apache? ango

Your message for list seminar has been rejected. The message is thus sent back to you. Your message : Received: from utia.cas.cz (ti311110a000-0132.dialup.online.no [130.67.247.132]) by visla.utia.cas.cz (8.12.9/8.12.9) with ESMTP id i3DIdQ6B010301 for <seminar@utia.cas.cz>; Tue, 13 Apr 2004 20:39:27 +0200 (METDST) Message-Id: <200404131839.i3DIdQ6B010301@visla.utia.cas.cz> From:

Hi, In the PPC backend, there is a "helper" class used to define instructions that implicitly define a condition register: class isDOT { list<Register> Defs = [CR0]; bit RC = 1; } and this gets used on instructions such as: def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), "addic. $rD, $rA, $imm", IntGeneral,

On Apr 12, 2013, at 2:06 AM, Hal Finkel <hfinkel at anl.gov> wrote: > In the PPC backend, there is a "helper" class used to define instructions that implicitly define a condition register: > > class isDOT { > list<Register> Defs = [CR0]; > bit RC = 1; > } > > and this gets used on instructions such as: > > def ADDICo : DForm_2<13,

Hi All, I have faced decoding conflict of DisassemblerTables from TableGen. I have instructions with same encoding and different mnemonic among different architecture versions. I have used Predicates and AssemblerPredicates to distinguish them on Codegen and Assembler but it does not work on Disassembler. When I look at TableGen/FixedLenDecoderEmitter.cpp, once there is decoding conflict,

Hello, I run into a problem that llvm can't write the correct ELFHeaderEFlags for hexagonv4. The following patch can fix it. Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp (revision 265917) +++

----- Original Message ----- > From: "Jakob Stoklund Olesen" <stoklund at 2pi.dk> > To: "Hal Finkel" <hfinkel at anl.gov> > Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> > Sent: Friday, April 12, 2013 11:36:49 AM > Subject: Re: [LLVMdev] TableGen list merging > > > On Apr 12, 2013, at 2:06 AM, Hal Finkel