similar to: [LLVMdev] New Alias Analysis Algorithm

Hi Hal, Thanks for your interest. We tested with the following existing compiler optimizations in LLVM with SPECINT2006 benchmarks: -dse (dead store elimination), -gvn (global value numbering), -licm (loop invariant code motion), -bb-vectorize (basic block vectorization), -memcpyopt (memcpy optimization), -sink (code sinking), -loop-idom (recognize loop idioms), -argpromotion (argument

Hi Daniel, I want to clarify that our analysis is not based on CFL-reachability. We apply CFL-reachability to matching context information where the exist from a function to a call-site must match the entry from the corresponding call-site. The problem is a simple balanced parentheses problem in CFL-reachability, and it can be computed efficiently. The paper you mentioned is a very nice paper

I notice you guys formulate your CFL reachability problem as a balanced parentheses problem. What algorithm do you use to solve it? Are you aware of recent work that comes up with linear time and n log n time algorithms to solve this class of problems: http://www.cse.cuhk.edu.hk/lyu/_media/paper/pldi2013.pdf In particular, the time bound from the paper: "However, if we need the precise

On Fri, Oct 18, 2013 at 7:27 AM, lian li <lianli at gmail.com> wrote: > Hi Daniel, > > I want to clarify that our analysis is not based on CFL-reachability. > We apply CFL-reachability to matching context information where the > exist from a function to a call-site must match > the entry from the corresponding call-site. Yes, sorry, I pulled the wrong quote, it was late.

Hi George, After digging a little deeper, it appears that readonly calls showing up as MemoryDefs is only happening on an EarlyCSE test that is using the new pass manager (test/Transforms/EarlyCSE/basic.ll test5 if you’re curious), so I suspect it is an issue with the new pass manager setup code for either MemorySSA, my changes to EarlyCSE, the test run command line or something else not

1) Sounds good. This isn’t holding me up so I’ll just try to keep an eye out for these changes. 2) I’ve attached an example IR file and debug log of where the caching is going bad. It depends on my changes to EarlyCSE, but hopefully it is clear from the debug output what is going on. Let me know if there is a better way to get this repro case to you. Also, I’ll be on IRC for the

DeaRs, I have a doubt about: BIC (Bayesian Information Criterion) SBIC (Schwartz Bayesian Informarion Criterion) SIC (Schwartz Information Criterion) In many references these are know as the same (eg. stepAIC() function) but I just found a SAS8.2 output that show either the BIC and SIC values for a logistic regression.. simillary values but different. 1) question: What are the differences?

Hello, I am a newbie. I can run the following code stored in "test.txt" without error using my XP machine: x <- scan("C:\\Rwork\\A.txt") x10 = filter(x, rep(1/10,10), sides=1) x x10 for(i in 10:length(x)){ if (x[i] > x10[i]) diff[i]="b" else diff[i]="s" } However, if I run it in another PC that uses Windows 7, the following error occurs:

On 9 February 2017 at 17:31, Amara Emerson <amara.emerson at gmail.com> wrote: > Ping. Does anyone else have thoughts on this? Hi Amara, It seems the people who replied in this thread are mostly in sync with the proposal, why don't you push a review in phab, and let's take this to the next level? cheers, --renato

Amara, first, thank you for answering. but I found expandPsuedo instructions actually happens before post-RA, like the following code showing: your approach is a little hacky, right? : ) // Expand pseudo instructions before second scheduling pass. addPass(&ExpandPostRAPseudosID); printAndVerify("After ExpandPostRAPseudos"); // Run pre-sched2 passes. if (addPreSched2())

Hello, Is there any exist LLVM Target (backend) that support PC relative load and store? If so, what exactly is the instruction? Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20191204/c345ac5c/attachment.html>

Folks, For some reason, all new phabricator diffs are automatically including Amara, which is probably a bit annoying for him, but pointless. I believe it happens because his name is the first in the alphabetical order. Can someone have a look at what's going on? cheers, --renato

Yes, SVE can vectorize early exit loops by using speculative (first-faulting) loads, which essentially give a predicate of the lanes loaded successfully. For uncounted loops with these special loads, the loop predicate tests can be done using a 'ptest' instruction, checking if the last element is active. Amara On 3 February 2017 at 10:15, Simon Pilgrim <llvm-dev at redking.me.uk>

I knew I'd regret leaving that option in for the MIPS port back in 99. Basically this is the only acceptable way for mcpu to exist, but should never have been added to the GCC aarch64 port at all since there's no compatibility with existing build systems to worry about. I would still like you to show this mythical piece of software that needs this compatibility. -eric On Jan 8, 2014 3:06

I’ve put up a patch here: https://reviews.llvm.org/D79769 <https://reviews.llvm.org/D79769> that adds a unified pipeline that targets can opt-into. It has some similarities with forcing fallbacks, but uses a different mechanism to do so to preserve the abort behavior. It therefore requires that every GISel pass needs to explicitly check whether the GISel selector is being requested rather

What I meant was to write your own expansion pass and run it after the scheduler passes, e.g. in the pre-emit stage. > if (addPreEmitPass()) printAndVerify("After PreEmit passes") Though if it's too hacky for you then fair enough. Amara On 23 November 2013 03:17, Liu Xin <navy.xliu at gmail.com> wrote: > Amara, > > first, thank you for answering. but I found

FYI all: the patch to enable it is available to review here: https://reviews.llvm.org/D41362 Thanks, Amara > On Dec 18, 2017, at 5:44 PM, Amara Emerson via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Ok. We’ll look at what we can do to further stress test it in the next two months, additional suggestions from the community is welcome. Patch should be incoming to enable it

Hi all, For GlobalISel, we’re exploring options for implementing inlining optimizations for memcpy and friends. However, looking around the existing implementation, I don’t see anything that would particularly be problematic for us to do it at the IR level. The existing TLI hooks to specify how certain memcpy calls should be lowered doesn’t have anything too SelectionDAG specific, and an IR

I think this after a second. I got your point. I can define a pseudo instruction for an instr-pair and expand it after post-RA-sched. as you said, in preEmitPass. The original intrinsic can also be kept. I just convert the intrinsic to pseudo instruction in TargetLower. Thank you for your enlightening suggestion! thanks, --lx On Sat, Nov 23, 2013 at 8:37 PM, Amara Emerson <amara.emerson at

I don’t know of any further issues preventing us flipping the switch. At this point, I’d aim to flip the switch shortly after the creation of the 6.0.0 release branch, so that GlobalISel can harden a bit more enabled-by-default on trunk before it goes into an LLVM release (presumably 7.0.0 then). Thanks, Kristof > On 11 Dec 2017, at 17:08, Amara Emerson <aemerson at apple.com> wrote: