similar to: [LLVMdev] Load/Store Instruction Error

Hi all, All of the data types are 32 bits and the pointer is 32 bit. Therefore, I need word adressing instead of byte adressing to use 8 GB memory. I was told that R600 uses word adressing and I looked at its codes but I could not find where the backends handles word adressing. Do you have any ideas about it? Thanks in advance. -------------- next part -------------- An HTML attachment was

Dear all, I want to compute the average of the three blocks for each x-variable which is equal slide in the code below. How can I do that ? block x1 x2 x3 x4 x5 1 23 22 23 24 23 1 21 25 26 21 39 1 23 24 22 23 23 2 20 21 23 24 28 2 32 23 34 24 26 2 19

I have a back end which has both scalar and vector registers that alias each other. I'm having a problem generating the ISel from tablegen that appears only when a vector register class is declared to contain integer vectors. At that moment tablegen doesn't seem to be able to infer integer types in patterns that it was able to before, but I'm not clear on why that's the

On Sun, 22 Apr 2007, Christopher Lamb wrote: > I have a back end which has both scalar and vector registers that > alias each other. I'm having a problem generating the ISel from > tablegen that appears only when a vector register class is declared > to contain integer vectors. At that moment tablegen doesn't seem to > be able to infer integer types in patterns that it was

On Thu, 04 Jun 2009 22:55:04 +0200, Pertti Kellomäki <pertti.kellomaki at tut.fi> wrote: > Hi Adam, > > John is right, the TCE stuff would be useful for you. Our > compiler targets a processor template that the designer can > populate pretty freely. The compiler then reads the architecture > description and creates an LLVM backend on the fly. > > Please don't

On Apr 18, 2007, at 2:07 PM, Evan Cheng wrote: > > On Apr 18, 2007, at 11:25 AM, Christopher Lamb wrote: > >> I noticed that the TableGen code emitter generator assumes that >> the instruction fields are declared in the instruction format in >> the same order that operands are defined. This seems like a bad >> dependence to me, and that TableGen should match

I've been testing my multi-stream mux directshow filter. And have created some files with 2 tracks of vorbis... varying from 2 mp3s transcoding to vorbis interleaved to one mp3 transcode to vorbis in one stream, and live muxed spoken audio encoded to vorbis in the other. Simliarly some with vorbis in one stram and speex encoded voice-overs in the other. My directshow filters can play these

Hi there, I am currently trying to create an LLVM Backend for a RISC architecture and running into problems with setCC and brcond. First a few explanations: The architecture doesn't have a dedicated flag register, but seven 1-bit-wide so called "condition registers", c0-c6, which can be set by e.g. a compare instruction: > cmp ne, c0, r1, 123 It also supports conditional

Hi all, I am trying to write a back-end for LLVM where any instruction may take any type of data. I am looking for the output to be of the format: inst.type reg1,reg2 etc. Where inst is the instruction, e.g. mov and type is data-type e.g. f32 etc. I tried creating a back-end with a register class which could take i32 and f32: def GPRegs : RegisterClass <"Test",

On Apr 23, 2007, at 5:06 PM, Chris Lattner wrote: > On Sun, 22 Apr 2007, Christopher Lamb wrote: >> I have a back end which has both scalar and vector registers that >> alias each other. I'm having a problem generating the ISel from >> tablegen that appears only when a vector register class is declared >> to contain integer vectors. At that moment tablegen

Digging deeper... 1. Is there a good reason that v2f32 types are excluded from the isFloatingPoint filter? Looks like a bug to me. v2f32 = 22, // 2 x f32 v4f32 = 23, // 4 x f32 <== start ?? v2f64 = 24, // 2 x f64 <== end static inline bool isFloatingPoint(ValueType VT) { return (VT >= f32 && VT <= f128) || (VT

Hi Adam, John is right, the TCE stuff would be useful for you. Our compiler targets a processor template that the designer can populate pretty freely. The compiler then reads the architecture description and creates an LLVM backend on the fly. Please don't hesitate to get in touch with us if you have questions. -- Pertti

Hi Adam, > One problem, I was trying to solve was, that I need to declare variables of let's say 5-bit width like 'i5 var', > the maximal bit-width may be limited to 64 bits. I need such variables to represent instruction's operands, > example is at the end this message. any standard compliant C compiler supports i5, believe it or not. Try this: #include

Hello gyus, I am working on a project, where we are trying to create a development environment for new ASIP processor design. Part of this project is a compiler generator, where we would like to generate C compiler from some instruction description. To keep it short, let's say, that in each instruction's semantics is described by some C code. What I would like to do is to compile this

On 1/22/20 1:18 PM, Daniel P. Berrangé wrote: > On Wed, Jan 22, 2020 at 01:01:42PM +0100, Michal Privoznik wrote: >> On 1/22/20 11:11 AM, Michal Privoznik wrote: >>> On 1/22/20 10:03 AM, R. Diez wrote: >>>> Hi all: >>>> >>>> I am using the libvirt version that comes with Ubuntu 18.04.3 LTS. >>> >>> I'm sorry, I don't

I just joined the list and appologize if this has been answered before but I am trying to interface between R and the Compaq Visual Fortran compiler version 6.6 for Windows. I found the following instructions on the web -- and an example. When I follow these directions exactly. R 2.0.0 crashes. Has anyone had any experience with this? Below are the instructions that I located: Thanks Dan

Hello again, I m trying to use timereg package as you suggested (R2.7.1 on XP Pro). here is my script based on the example from timereg for a fine & gray model in which relt = time to event, rels = status 0/1/2 2=competing, 1=event of interest, 0=censored random = covariate I want to test library(timereg) rel<-read.csv("relapse2.csv", header = TRUE, sep = ",",

On Apr 18, 2007, at 11:25 AM, Christopher Lamb wrote: > I noticed that the TableGen code emitter generator assumes that the > instruction fields are declared in the instruction format in the > same order that operands are defined. This seems like a bad > dependence to me, and that TableGen should match the name of field > declared in the instruction with the name of the

I noticed that the TableGen code emitter generator assumes that the instruction fields are declared in the instruction format in the same order that operands are defined. This seems like a bad dependence to me, and that TableGen should match the name of field declared in the instruction with the name of the operand in order to determine which operand of the MI to use . See

Need some guidance about the right way to model this -- how would you model a backend with a handful of read-only physical registers that are passed as arguments to a function? I was emitting copyFromReg nodes in the LowerFormalArgument() routine, but then the register allocator and coalescer are resisting coalescing the COPY MI's for various reasons - for example, the read-only register class