similar to: [LLVMdev] Partially complete LLVM backend for the VideoCore 4

On 5/29/14, 12:12 PM, Alex Bradbury wrote: [...] > Congratulations on the release David, this looks very interesting. I > had wondering what you were targeting given your series of questions > to the mailing list :) Yeah, it is a kind of distinctive architecture. Did I mention the condition codes? It's got condition codes... It's a lovely thing to write hand assembly in, by the

My architecture has an FPU, but uses integer registers to store floating-point values. So each register can store either an int or an IEEE float. I define a register class like this: def GR32 : RegisterClass<"MyArch", [i32, f32], 32, (sequence "R%u", 0, 32)>; So far so good. However, when I write a rule to store a register: def STORE32r : S32< (outs), (ins

Hi David, > [(set GR32:$rD, globaladdr:$addr)] > It seems to have somehow managed to create a cycle in the DAG, which is > of course wrong. But how? When I write a similar pattern into the ARM .td files and look at (from the build directory) lib/Target/ARM/ARMGenDAGISel.inc, I see: /*56478*/ /*SwitchOpcode*/ 13, TARGET_VAL(ISD::GlobalAddress),// ->56494 /*56481*/

> Maybe this would make a good GSOC project. It's definitely too small project for a GSoC. One can try to start from https://github.com/asl/llvm-openrisc (openrisc branch inside), however, it's already 2 years old... -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State Universit

I'm having a great deal of trouble figuring out how to write instruction patterns which actually match the DAG produced by the compiler. I can't seem to find any documentation on both what the various nodes represent or on what the syntax accepted by TableGen is. The backends I have access to all seem to do this in different (and obscure) ways. And when things go wrong the compiler seems

On 8 March 2014 00:53, Owen Anderson <resistor at mac.com> wrote: > ISDOpcodes.h contains what documentation there is on the semantics of each > opcode. And TargetOpcodes.h for a few of the post-ISel ones (mostly they're in MachineInstr form, but you'll see them with -view-sched-dags, and occasionally before). Tim.

I've mentioned my sneaky plans to target the MOS6502 here before. The big issue I think is that a lot of instructions don't really have a choice for output register. It all just goes into the accumulator, X index, or Y index based on the specific instruction. So, my question is, when I'm defining my ins, outs and registers for these instructions, is it going to be a problem that

Hi folks out there, I'm new to this project but very keen on more information. The reason I want to have Wine, is because I want to get "Klingon Academy" on OS X. On every Windows Revision above Win 98 the game fails, so I thought: "Why not do it the other way around and try Wine?" So, here I am. And after the first look into the Wiki page, I was VERY confused on how I

I vote for spec''ing. Anybody else?

Hi, I submitted Fruity Loop 7 to the AppDB and it got accepted and then after a little while it got deleted. I don't know why as the notification did not give a reason. Anyway, I've been testing it with .9.41 and a lot of the issues have been resolved. Sound latency is not a problem. In version .9.40 sampling/sound latency was an issue; now, WINE does a better job than XP.

Hi, i'm trying to compile R on a Cray XT3 using pgi/7.2.1 - CNL (compute node linux) The R version is 2.8.0 this is the option -enable-R-static-lib=yes --disable-R-shlib CPICFLAGS=fpic FPICFLAGS=fpic CXXPICFLAGS=fpic SHLIB_LDFLAGS=shared --with-x=no SHLIB_CXXLDFLAGS=shared --disable-BLAS-shlib CFLAGS="-g -O2 -Kieee" FFLAGS="-g -O2 -Kieee" CXXFLAGS="-g -O2

I have a simple expression-evaluation language using LLVM (it's at https://cowlark.com/calculon, if anyone's interested). It has pretty primitive support for 3-vectors, which I'm representing as a <3 x float>. One of my users has asked for proper n-vector support, and I agree with him so I'm adding that. However, he wants to use quite large vectors. He's mentioned 30

I'd like my compiler to emit proper line number information. The docs talk about Instruction::setDebugLoc(), but that method doesn't actually have to be in my 2.7 LLVM Debian package. What's the correct way of doing this? In addition, can anyone point me at an example of how to emit a comment attached to an instruction (or function)? -- ┌─── ｄｇ＠ｃｏｗｌａｒｋ．ｃｏｍ ─────

Dear R-users, I'm trying to model some data using a tweedie GLM approach. My response variable is the number of pupae that are the offspring of a subordinate wasp on a wasp's nest. However, they're not count data- for each nest, I only know the mean number of pupae per subordinate, which is continous. The data also contain a high proportion of zeros. I'm not very experienced at

I'm using the Debian LLVM package to try and do JIT on a Linux armhf device. Unfortunately it seems to be generating armel code rather than armhf code, and since the ABIs don't match nothing works. I've tried overriding the triple to arm-unknown-linux-gnueabihf and arm-linux-gnueabihf (via module->setTargetTriple), and while the triples are accepted, the actual generated code

Hello all, I am hoping to use survival analysis to examine whether parasite attack increases nest death in a species of social wasp. I therefore have data for 1. Whether the nest "died" in the 6 week census period ("Status", where 1=died, 0=survived) 2. The day number of death/last recorded day it was observed alive. 3. Whether the nest was attacked by the parasite (0/1 as

On 20/01/13 19:20, Caldarale, Charles R wrote: [...] > That's because there is no llvm.ceil.* intrinsic defined in include/llvm/Intrinsics.td for 3.2 Ah. Yes, that would explain it... does this mean that I can rely on all the intrinsics listed existing for the common types (int, float, double)? Or should I be trying to follow the libc call route? I've noticed that llc is successfully

I'm working on an LLVM-based compiler for a very closure-centric language. It's becoming apparent that it's going to suffer heavily from garbage collector churn, as all the useful programming idioms the language makes possible are going to involve memory allocations, either to create objects or to allocate storage for upvalues. However, it's possible to optimise away a lot of heap

On 18/06/2014 04:17, Charles Lepple wrote: > On Jun 13, 2014, at 2:53 AM, Giuseppe Corbelli <giuseppe.corbelli at copanitalia.com> wrote: > >> As said in previous mail, I just finished a first working version of a driver for the UPS found on ASEM PB1300 device >> (http://www.asem.it/prodotti/industrial-automation/box-pcs/performance/pb1300/) >> Linux only, accessed

On 2 September 2010 11:35, David Given <dg at cowlark.com> wrote: >> The docs >> talk about Instruction::setDebugLoc(), but that method doesn't >> actually appear to be in my 2.7 LLVM Debian package. I suggest you getting the SVN code, since quite a lot has changed since last freeze. -- cheers, --renato http://systemcall.org/ Reclaim your digital rights, eliminate