similar to: [LLVMdev] How to 'define and use' a LOOP intrinsic that takes "iteration count" and the "label" to jump to ?

Hello. I come back to this thread. But I want to ask a slightly different question. Is there a way to have LLVM IR language intrinsics that are given at construction time a string that is written at assembly generation time as it is? (so, basically having placeholders of strings in LLVM that remain untouched until the end, including code generation time.) More exactly, I would

Hi Alex, You might find it useful to look at how lib/Target/PowerPC/PPCCTRLoops.cpp works. -Hal ----- Original Message ----- > From: "Alex Susu via llvm-dev" <llvm-dev at lists.llvm.org> > To: "llvm-dev" <llvm-dev at lists.llvm.org> > Sent: Monday, May 30, 2016 5:09:37 PM > Subject: [llvm-dev] Back end with special loop instructions > > Hello.

Hello. I'm writing a back end for my research SIMD processor that has an assembly language that is blocked structured, with one-level loops. An example program with my assembly language: REPEAT_X_TIMES(Param2) R0 = LS[offset_A]; END_REPEAT; The LLVM code somewhat equivalent to the above ASM program is: vector.body: %index = phi i64 [

On Mon, 5 Feb 2007, Dan Gohman wrote: > LLVM knows what all the types of the intrinsic functions are; I thought, > why are users (including llvm-gcc...) required to duplicate all this > information in order to use them? I mean in order to call > getOrInsertFunction to get declarations for them. That is an excellent question! :) In the bad old days, we used to allow intrinsics

LLVM knows what all the types of the intrinsic functions are; I thought, why are users (including llvm-gcc...) required to duplicate all this information in order to use them? I mean in order to call getOrInsertFunction to get declarations for them. So I wrote this patch, which allows all this code to be generated automatically. Is this a good approach? Dan -- Dan Gohman, Cray Inc. <djg at

The actual purpose that I wanted such an intrinsic is to solve a problem similar to this one in X86. Say I wanted to read the "mxcsr" register(which is the status register for SSE instructions) after a particular instruction, then I need a kind of barrier intrinsic which will not allow the arithmetic instructions to move around it. Or else I will be reading the status of some other

Here basically my problem is vector width since i have used v64i32 in my backend. now if vector width=64. i want the Reg_B class registers to be assigned and if vector width=2048 i want Reg_A registers to be assigned to instruction. Should i incorporate the solution in lowering stage? some thing like; addRegisterClass(MVT::v2048i32, &X86::Reg_B);

Hi, Arm have recently announced the v8.1-M architecture specification for our next generation microcontrollers. The architecture includes vector extensions (MVE) and support for low-overhead branches (LoB), which can be thought of a style of hardware loop. Hardware loops aren't new to LLVM, other backends (at least Hexagon and PPC that I know of) also include support. These implementations

is there any guarantee that the nvptx intrinsic "llvm.nvvm.barrier0" will not be moved around by opt ? In other words, can I expect all the instructions above "llvm.nvvm.barrier0" to remain above it and those below it to remain below, after all the opt passes are run ? If that is not the case, is there a way to define such an intrinsic ? Thanks. -------------- next part

I have written test.ll as below and ran 'opt' on it as " opt -std-compile-opts test.ll -S -o -" . But the output shows that there is code motion around the barrier intrinsics. test.ll ------- ; ModuleID = 'test.bc' define void @test(i16* %I_0, i16* %I_1, i16* %I_2, i16* %I_3, i16* %O_0) { entry: %T_0 = load volatile i16* %I_0 %T_1 = load volatile i16* %I_1 %T_2 =

hello, i have a situation where i have to assign the registers to instructions based on the loop iterations. for eg.. the registers are: R_0_V_0, R_0_V_1, R_0_V_2, R_0_V_3, R_1_V_0, R_1_V_1, R_1_V_2, R_1_V_3, R_2_V_0, R_2_V_1, R_2_V_2, R_2_V_3. These registers defined in object Reg_A These are total 12 registers. will use them contiguously, here i define it in above mentioned order i.e

Hello everyone, Consider we have this following set of code: int foo() { int a,b; a = __builtin_XX(0x11); b = __builtin_XX(0x11); return a+b; } The problem currently is that LLVM eliminated the second call and copied the result from the first call into a new set of registers. Is there is a way to force LLVM to generate two explicit calls to a builtin function. The builtin takes in an integer

On Wed, Jul 25, 2012 at 12:48 AM, Michele Scandale <michele.scandale at gmail.com> wrote: > Dear all, > > I'm working on an exploratory backend on llvm. In the instruction set I'm using > I have an instruction (called DECJNZ) that decrements a register and, if the > decremented value is not zero, jumps (with a relative jump) to a given offset. > > I've

Dear all, I'm working on an exploratory backend on llvm. In the instruction set I'm using I have an instruction (called DECJNZ) that decrements a register and, if the decremented value is not zero, jumps (with a relative jump) to a given offset. I've described in tablegen this instruction as follow: def DECJNZ : Instruction { let Namespace = "MyTarget"; let

Hi all,I'm working on my own backend for a custom CPU. I have defined paired registers for 64bit operations, however to set a 64bit paired register with 64bit immediate I have to set each register in that pair separately with the higher and the lower 32bits of the immediate. Could anyone give me an advice how to describe it in *InstructionInfo.td or point me to something similar in the LLVM

Il 25/07/2012 10:07, Eli Friedman ha scritto: > On Wed, Jul 25, 2012 at 12:48 AM, Michele Scandale > <michele.scandale at gmail.com> wrote: >> Dear all, >> >> I'm working on an exploratory backend on llvm. In the instruction set I'm using >> I have an instruction (called DECJNZ) that decrements a register and, if the >> decremented value is not

Hi Manuel, Here's another commit authored through the web interface where no discussion or reviewership information is apparent on the mailing list. All we see in cases like this are a few unthreaded list posts by the original author followed by an SVN revision number: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140714/226166.html For any patch that's submitted for

On 17/07/2014 20:27, Eric Christopher wrote: > Hi Alp, > > On Thu, Jul 17, 2014 at 6:25 AM, Alp Toker <alp at nuanti.com> wrote: >> Hi Manuel, >> >> Here's another commit authored through the web interface where no discussion >> or reviewership information is apparent on the mailing list. > If you look at the phab review, it's the same there. Does

<table cellspacing='0' cellpadding='0' border='0' ><tr><td style='font: inherit;'>Hi,<br>I tried creating intrinsics which are to be<br>placeholders for a set of instructions (actually a section of a basic block) to be executed elsewhere(for e.g. in HW).<br>These intrinsics are to take care of the data dependencies of the set of

I have a target backend which is currently causing live interval analysis to throw 'Interval not live at use' errors for many of my benchmarks. I imagine that this is caused by missing information for my target (probably in the instructioninfo tablegen?), but I am having difficulties in both debugging and fixing this problem, and would appreciate any advice or help anyone can give.