Displaying 20 results from an estimated 500 matches similar to: "[LLVMdev] Load Instruction that changes value of two registers"
2014 Sep 05
5
[LLVMdev] [PATCH] [MachineSinking] Conservatively clear kill flags after coalescing.
On Sep 5, 2014, at 10:21 AM, Juergen Ributzka <juergen at apple.com> wrote:
> clearKillFlags seems a little "overkill" to me. In this case you could just simply transfer the value of the kill flag from the SrcReg to the DstReg.
We are extending the live-range of SrcReg. I do not see how you could relate that to the kill flag of DstReg.
Therefore, I still think, this is the
2017 Sep 19
1
Describing subreg load for vectors without using vector_insert
Hi,
We are using a vector_insert in our target, to describe an instruction
performing a lane-load of a vector register as:
set $dstReg, (vector_insert $dstReg, (load $addr)), imm:$lane)
However, this means that the dstReg is also marked as used in the
instruction, which we do not want. We can do a direct lane-load to a part
of the vector register without disturbing the rest, and hence would
2010 Jun 16
0
[LLVMdev] Simpler subreg ops in machine code IR
On Jun 15, 2010, at 2:48 PM, Jakob Stoklund Olesen wrote:
> I am considering adding a new target independent codegen-only COPY instruction to our MachineInstr representation. It would be used to replace INSERT_SUBREG, EXTRACT_SUBREG, and virtual register copies after instruction selection. Selection DAG still needs {INSERT,EXTRACT}_SUBREG, but they would not appear as MachineInstrs any longer.
2015 Sep 29
3
Duplicating node in SelectionDAG?
It appears that it's impossible to duplicate a node in the dag. For
example, there is some code:
b = a * a; // a is a global int
A LD node is generated for A and it goes into both Operand 0 and 1 of the
MUL node. The issue is I'm trying to match a pattern of:
set dstReg:$dstD (OpNode (srcAType (load addr32:$srcA)), (srcBType (load
addr32:$srcB)))
so basically a mem, mem, reg
2014 Oct 22
2
[LLVMdev] Fetching the functions in C files
Thanks Markus.
Having llvm-as to turn the extracted function.bc file to .ll caused an
error saying:
*llvm-as-3.4: function_bc:1:1: error: expected top-level entity*
*BC! #AI29bEBB2I (some more binary)*
This error is just the same error that I received while using llvm-extract
on a .c file (not .bc or .ll).
Do I have to include other things in the command ? I mean generating a
function.ll
2010 Jun 15
4
[LLVMdev] Simpler subreg ops in machine code IR
I am considering adding a new target independent codegen-only COPY instruction to our MachineInstr representation. It would be used to replace INSERT_SUBREG, EXTRACT_SUBREG, and virtual register copies after instruction selection. Selection DAG still needs {INSERT,EXTRACT}_SUBREG, but they would not appear as MachineInstrs any longer.
The COPY instruction handles subreg operations with less
2009 Jun 04
1
[LLVMdev] assertion in LeakDetector
Hi Bill,
I am using the following version of BuildMI :
MachineInstrBuilder BuildMI(MachineFunction &MF,
const TargetInstrDesc &TID,
unsigned DestReg)
I do the following :
void createInstrs(std::vector<MachineInstr *>& ilist)
{
Machine Instr *mi;
mi = BuildMI(MF, someTID, somereg);
2014 Sep 05
3
[LLVMdev] [PATCH] [MachineSinking] Conservatively clear kill flags after coalescing.
Hi Quentin,
Jonas looked further into the problem below, and asked me to submit his patch. Note the we have our own out-of-tree target, and we have not been able to reproduce this problem on an in-tree target. /Patrik Hägglund
[MachineSinking] Conservatively clear kill flags after coalescing.
This solves the problem of having a kill flag inside a loop
with a definition of the register prior to
2012 Oct 06
2
[LLVMdev] Pairing Registers on a Target Similar to Mips?
I'm working on a target based on the MIPS target, and when I copy f64
values into 32 bit registers for calling functions, I need the operation to
work on a of 32 bit registers (because the language I'm translating to
isn't actually mips). I've been looking at how to do this, but I haven't
been able to figure it out. Since the Mips target code is still really
close to mine,
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
Here is the instruction in question:
multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass
srcAReg,
RegisterClass dstReg, ValueType srcAType,
ValueType dstType, Operand ImmOd, ImmLeaf imm_type>
{
def REG_REG : SetADInOut<asmstr, srcAReg, dstReg,
[(set dstReg:$dstD, (OpNode srcAReg:$srcA))]>;
def IMM_REG :
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
1. MOV16Copy_IMM_REG is the instruction matched, sorry. AD is the
multiclass. The IMM in my case is a global. So you can see that
GPRBaseRegs, GPRBaseRegs sets the registerclass for both the src and dst
operands, in this case (MOV16Copy_IMM_REG) it's the dst.
2. Yes I agree, it most likely would.
Honestly, this comes across like a bug, or unintended feature. It's adding
an extra COPY to
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
I have not tried 3.5, it's a significant amount of work to port from one
version to the next though, I did not personally do the 3.4 to 3.6 porting.
I agree though, it was very strange that it suddenly just changed behavior.
It looks like to me that InstrEmitter.cpp:getVR is the one assigning the
virtual register no?
Though this code in CreateVirtualRegisters:
const TargetRegisterClass *RC
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
AddRegisterOperand calls getVR and yes, I think an IMPLICIT_DEF is being
generated.
On Tue, Aug 25, 2015 at 2:40 PM, Quentin Colombet <qcolombet at apple.com>
wrote:
>
> On Aug 25, 2015, at 11:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote:
>
> I have not tried 3.5, it's a significant amount of work to port from one
> version to the next though, I did not
2017 Feb 15
5
Unsigned int displaying as negative
Where does the unsignedSub come from?
On 2017-02-15 20:38, Ryan Taylor wrote:
> Sorry, it should be:
>
> defm SUB16u_ : ABD_NonCommutative<"sub16u", unsignedSub, LOADRegs,
> GPRRegs, DSTRegs, i16, i16, i16, uimm16, immZExt16x>;
>
> On Wed, Feb 15, 2017 at 2:37 PM, Ryan Taylor <ryta1203 at gmail.com>
> wrote:
>
>> I see. If I put simm16 and
2015 Apr 23
4
[LLVMdev] IRBuilder and "ad hoc" optimizations
Hi LLVM,
IRBuilder can fold constants (that behaviour can be controlled by Folder
type). What do you think about optionally allow IRBuilder to eliminate
no-op instructions like `add %a, 0` or `memcpy(%a, %b, 0)`?
- Paweł
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2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
BB#0: derived from LLVM BB %entry
%vreg0<def> = MOV16Copy_IMM_REG <ga:@a+1>[TF=1]; GPRRegs:%vreg0
%vreg1<def> = COPY %vreg0; PTRRegs:%vreg1 GPRRegs:%vreg0
Send_iii %NULLR0, %vreg1<kill>, 1, 1, 1, 1, 0; PTRRegs:%vreg1
RetRA
This is what I get. This is what I'd like to get:
BB#0: derived from LLVM BB %entry
%vreg0<def> = MOV16Copy_IMM_REG
2009 Jun 04
2
[LLVMdev] assertion in LeakDetector
I am seeing the following assertion in leak detector.
/llvm/lib/VMCore/LeakDetector.cpp:43:
void<unnamed>::LeakDetectorImpl<T>::addGarbage(const T*) [with T =
void]: Assertion `Ts.count(Cache) == 0 && "Object already in set!"'
failed.
I am creating a list of instructions using BuildMI() and adding them
to a basic block using BB->insert(). I am seeing this
2009 Jun 04
0
[LLVMdev] assertion in LeakDetector
On Wed, Jun 3, 2009 at 5:10 PM, Manjunath Kudlur <keveman at gmail.com> wrote:
> I am seeing the following assertion in leak detector.
>
> /llvm/lib/VMCore/LeakDetector.cpp:43:
> void<unnamed>::LeakDetectorImpl<T>::addGarbage(const T*) [with T =
> void]: Assertion `Ts.count(Cache) == 0 && "Object already in set!"'
> failed.
>
> I am
2012 Oct 09
0
[LLVMdev] Pairing Registers on a Target Similar to Mips?
Ryan,
I don't think I fully understand the problem you described, but please see
the comments below.
Hope this helps you solve the problem.
On Sat, Oct 6, 2012 at 3:18 PM, ryan baird <ryanrbaird at gmail.com> wrote:
> I'm working on a target based on the MIPS target, and when I copy f64
> values into 32 bit registers for calling functions, I need the operation to
> work
2017 Feb 15
4
Unsigned int displaying as negative
I see. If I put simm16 and immSExt16x in place of uimm16 and immZExt16x
respectively, the imm matches but it prints out -32768 (which is invalid
for sub16u). We are using uimm16 not match unsigned but for PrintMethod,
effectively uimm16 and simm16 are both Operand<i16>. I'm still unclear why
simm16 matches and uimm16 does not. Here is the pattern if that helps at
all.
So just as a