similar to: [LLVMdev] Order of glued nodes during scheduling

Hi, I'm getting an Instruction emitter crash when emitting an INLINEASM SDNode that is Glued to other nodes. The crash happens at line 808 of file llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp: const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); with the assertion: assert(isMachineOpcode() && "Not a MachineInstr opcode!"); I'm not a great expert

I've been goofing with this all day with 2.0.15 and I'm starting to realize that either a) I'm not that smart, b) it's been so long since I messed with namespaces that I'm going about it completely wrong, or c) it's just not possible. I haven't posted 'doveconf -n' and other details, because mainly I'm just looking for 'yes, this is possible' or

Hello, I've hit an assertion in SelectionDAG where we try to merge 2 loads that have the same operands but their MMO flags differ. One is dereferenceable and one is not. I'm not sure what the underlying issue here is: 1) MDSDNode with the same operands should have the same flags set on their respective MMO. The fact the flags differ when the opcode,types,operands and address-space are

The following commit seems to have added a dependency on glu but does no checks to see if it is actually available: commit fa5bf5754d8a2e47d659a3abe5cb59a7b0e304d7 Author: David Reveman <davidr@novell.com> Date: Tue Jan 16 06:07:39 2007 +0100 Project vertices and only update minimum required destination texture region. Some more optimizations should be done here but the current

i have been compiling wine from git regularly with no problems whatsoever until now. ./configure now always spits out not found messages for -lGL and -lGLU. opengl and direct3d support cannot be enabled. how do i fix that. i'm on fedora 11 with nvidia 190.32 drivers. thanks for any help i can get.

After PrologEpilogCodeInserter I found that the instructions that restore callee saved registers S0,S1,LR are in the wrong location ,the instructions are: %S0<def> = LD %SP, 36; mem:LD4[FixedStack2] %S1<def> = LD %SP, 40; mem:LD4[FixedStack1] %LR<def> = LD %SP, 44; mem:LD4[FixedStack0] (LR is the Return address register) the whole code of print-machineinstrs are: # After

Hello all, I am working on adding atomics support to the AVR backend. Because the target can only have one core, it is sufficient to: - Save the status register - Disable interrupts - Do the nonatomic LOAD/STORE/SWAP/ADD - Restore the status register I’d really like to be able to do this at the IR level. What I want to do is write a custom lowering hook to convert ISD::ATOMIC_LOAD

Hello, I am trying to run a small application called Miku Desktop Mascot. a small anim character dancing on the screen (nice distraction when all day on code lines). current system is : Fedora 13 x64 Nvidia GTX 460 , proprietary driver 260.19.12 Wine 1.3.5 x64 I actually am a java developer (not c++) so if I can be of any help testing, compiling wine on my machine it's possible. thanks

Hello, I am getting this error. What instruction is required to be implemented? LLVM ERROR: Cannot select: t22: v32i32 = vselect t724, t11, t16 t724: v32i32,ch = load<LD128[FixedStack1]> t723, FrameIndex:i64<1>, undef:i64 t659: i64 = FrameIndex<1> t10: i64 = undef t11: v32i32,ch = load<LD128[%sunkaddr45](align=4)(tbaa=<0x481f1e8>)> t0, t8, undef:i64

Hi, I'm trying to understand how virtual regs are assigned to operands in IR instructions. I looked into SelectionDAG but could not figure out where the assignment happens. How and where does this conversion happen? Furthermore, I want to build a map between variable and the virtual register (x corresponds to vreg11 in below code). I've been stuck here for a while. Any help is greatly

Hi, Apologies this is a bit lengthy. TLDR: I'm using Dragonegg + LLVM 3.2 and uClibc, and am finding that using the Fast register allocator (i.e. -optimize-regalloc=0) causes miscompilation of setsockopt calls (5-arg system calls). The problem doesn't happen with the default register allocation path selected. It can be worked around by manually simplifying the system call setup