similar to: [LLVMdev] ARM integrated assembler generates incorrect nop opcode when switching from arm to thumb mode

Hi Michael, Overall patch looks good. I do have a few comments below. My main comment is please try to make the style match that used in the MCMachOStreamer more closely. I intend to refactor more functionality into the base MCObjectStreamer class, and having them use consistent idioms makes this easier; specific instances are included in the comments: -- > diff --git

Hi Jim, The diff below is not intended to be a patch, but a starting point. It is the shortest path (I hope) to getting LLVM to emit ARM mapping symbols to the ELF without changing any shared interfaces. Could you have a look at the FIXME comments and offer some pointers on how to get this code out of MCELFStreamer? Thanks, Greg diff --git a/lib/MC/MCELFStreamer.cpp b/lib/MC/MCELFStreamer.cpp

Hi Jonas, > here is a patch to add Thumb call relocation to the dynamic linker. I would be happy if you could commit it to the SVN. Thanks very much for working on this. It looks like a good starting-point, but there are a couple of issues with the patch at the moment. First, it only handles RelValue up to 22 bits (depending on how you count) in size. But on ARMv6T2 onwards the J1 and J2

This would be best reported to Apple's Radar bug database at http://bugreport.apple.com/ but its whole website has been down for a while. I have a 100% reproducible Thumb-2 code generation error that occurs at all of the levels of optimization available in the Xcode 4.2 for Snow Leopard build settings GUI: -O0, -O1, -O2, -O3 and -Os. However the bad machine code only occurs in Release

splited patches and test cases mc-elf-thumbfunction-bit.diff: for 1 mc-elf-arm-backend-bl-blx-sign-bit.diff: for 2. mc-elf-thumb-bl-blx-relocation-table-entry.diff: for 3. mc-elf-cpu-xscale-attributes.diff: for 4. elf-thumbfunc.s: test case for 1 elf-thumbfunc-reloc.ll: test case for 2 and 3 elf-xscale-attribute.ll: test case for 4 On Fri, May 13, 2011 at 1:42 PM, Koan-Sin Tan <koansin.tan

On 11-05-16 09:21 AM, Koan-Sin Tan wrote: > splited patches and test cases > > mc-elf-thumbfunction-bit.diff: for 1 > mc-elf-arm-backend-bl-blx-sign-bit.diff: for 2. > mc-elf-thumb-bl-blx-relocation-table-entry.diff: for 3. > mc-elf-cpu-xscale-attributes.diff: for 4. > > elf-thumbfunc.s: test case for 1 > elf-thumbfunc-reloc.ll: test case for 2 and 3 >

On Tue, May 17, 2011 at 12:29 AM, Rafael Avila de Espindola <rafael.espindola at gmail.com> wrote: > On 11-05-16 09:21 AM, Koan-Sin Tan wrote: >> >> splited patches and test cases >> >> mc-elf-thumbfunction-bit.diff: for 1 >> mc-elf-arm-backend-bl-blx-sign-bit.diff: for 2. >> mc-elf-thumb-bl-blx-relocation-table-entry.diff: for 3. >>

Hi Tim, Thank you for clarifying what the error actually means! I did read something about the BLX instruction but since I'm compiling strictly for thumb, it didn't make much sense to me. Adding -mdisable-tail-calls as a cc1 command indeed allowed me to link the generated binary. After looking some more at the ld64 source code, I came across the following comment: // The tail-call

On 17 October 2012 15:05, Greg Fitzgerald <garious at gmail.com> wrote: > + virtual void EmitMappingSymbol(bool IsData); I'd use an enum, or have multiple internal implementations... EmitDataMappingSymbol -> { nop on base class, on ARM, prints "$d" } EmitCodeMappingSymbol -> { nop on base class, calling either EmitThumbMappingSymbol or EmitARMMappingSymbol (private)

As part of my ELLCC project (http://ellcc.org), I build clang/LLVM on my native x86_64 Linux box and then use it to compile itself. For further sanity checking, I then use that copy to cross compile for other targets (arm, armeb, i386, microblaze, mips, mipsel, ppc, and x86_64). After updating to a recent TOT revision, r195452, I get a strange error when cross compiling for the i386:

Thanks Renato. I'm finishing up a patch for this and will post it to llvm-commits. But one concern, to create an ARMELFStreamer as you recommend, I had to move MCELF.h to "include/llvm/MC" and added a MCELFStreamer.h to the same directory. That okay to do? -Greg On Wed, Oct 17, 2012 at 7:22 AM, Renato Golin <rengolin at systemcall.org>wrote: > On 17 October 2012

> ecc: note: diagnostic msg: /tmp/ARMAsmBackend-265222.cpp > ecc: note: diagnostic msg: /tmp/ARMAsmBackend-265222.sh > ecc: note: diagnostic msg: > > ******************** > The error only occurs for i386. Any ideas? Open a bug report with ARMAsmBackend-265222.cpp and ARMAsmBackend-265222.sh? Cheers, Rafael

I saw this; http://bb.pgr.jp/builders/clang-3stage-cygwin Not sure, though, r195406 triggered this issue. I am still investigating. I guess it could be reproducible with -target i686-* on other hosts. 2013/11/25 Rafael Espíndola <rafael.espindola at gmail.com>: >> ecc: note: diagnostic msg: /tmp/ARMAsmBackend-265222.cpp >> ecc: note: diagnostic msg:

On 16 March 2018 at 10:38, Peter Smith via llvm-dev <llvm-dev at lists.llvm.org> wrote: > On 15 March 2018 at 19:12, Friedman, Eli <efriedma at codeaurora.org> wrote: >> Having ARMv7a instructions in an ARMv4t file shouldn't be a problem: a >> function should be allowed to override the CPU attributes to generate code >> for a newer target. This is generally

On Wed, 15 Apr 2020 at 03:36, John Brawn <John.Brawn at arm.com> wrote: > > > Could you please point out what am I doing wrong in the patch ? > > It's because you're getting the function name by doing > callee->getName().str().c_str() > The str() call generates a temporary copy of the name which ceases to exist outside of this expression > causing the

On Sun, Jul 11, 2010 at 6:10 PM, Chris Lattner <clattner at apple.com> wrote: > This probably needs to be slightly tweaked to work with mainline.  I don't see anything objectionable, but I think Daniel needs to review this one. Updated patch to work with mainline. http://github.com/Bigcheese/llvm-mirror/commit/d19a4c82c18afc4830c09b70f02d162292231c94 - Michael Spencer

Hi Hal, Thanks for the reference. I’ve looked at PPCBranchSelector and the PowerPC backend. It is very different from the X86 architecture and unfortunately the way branch relaxation and alignment related issues are handled in PPC cannot be copied to X86. This is because: 1. PPC instructions are of fixed length while X86 instructions are of variable length, and their length can change

Thanks for the example, that is very useful in working out the overall scope of the problem, which is now wider than I thought it was. I've put some comments inline. On 15 March 2018 at 19:12, Friedman, Eli <efriedma at codeaurora.org> wrote: > On 3/15/2018 9:43 AM, Peter Smith via llvm-dev wrote: >> >> Hello everyone, this is most likely Arm specific, but could affect

Hi Mayur, > On 24 Nov 2014, at 07:00, MAYUR PANDEY <mayur.p at samsung.com> wrote: > In the assembly generated with O0, we are getting the "blx" instruction whereas with O1 we get "bx" (in 3.4.2 we used to get "blx" for both O0 and O1). > > Is this because of this patch: [llvm] r214959 - ARM: do not generate BLX instructions on Cortex-M CPUs

Hi, I've run Clang Static Analyzer checker alpha.cplusplus.NewDeleteLeaks over LLVM codebase to detect false-positives and at the same time eliminate memory leaks. The majority of leaks were detected in lib/Target/* and lib/MC/*. In all cases the similar trick was detected as a leak (example from lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp) : static MCStreamer