Displaying 20 results from an estimated 2000 matches similar to: "[LLVMdev] [PATCH] Making Type::getScalarSizeInBits() const"
2012 Oct 19
11
[LLVMdev] Predication on SIMD architectures and LLVM
Hello,
I'm working on a compiler based on LLVM for a SIMD architecture that
supports instruction predication. We would like to implement branching
on this architecture using predication.
As you know the LLVM-IR doesn't support instruction predication, so I'm
not exactly sure on what is the best way to implement it.
We came up with some ways to do it in LLVM:
- Do not add any
2012 Oct 19
0
[LLVMdev] Predication on SIMD architectures and LLVM
We are currently doing something similar to your third option in Hexagon
backend. But it is a VLIW so predication is not the only reason for that.
Sergei
---
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> On Behalf Of Marcello
2012 Oct 19
0
[LLVMdev] Predication on SIMD architectures and LLVM
On Fri, Oct 19, 2012 at 04:38:29PM +0100, Marcello Maggioni wrote:
> Hello,
> I'm working on a compiler based on LLVM for a SIMD architecture that
> supports instruction predication. We would like to implement
> branching on this architecture using predication.
> As you know the LLVM-IR doesn't support instruction predication, so
> I'm not exactly sure on what is the
2013 Oct 21
0
[LLVMdev] Instruction Emitter crash when emitting glued InlineAsm SDNode
Hi,
I'm getting an Instruction emitter crash when emitting an INLINEASM
SDNode that is Glued to other nodes.
The crash happens at line 808 of file
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp:
const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
with the assertion:
assert(isMachineOpcode() && "Not a MachineInstr opcode!");
I'm not a great expert
2013 Sep 24
1
[LLVMdev] llvm/clang and 'odd bit types'
Hi all,
I recently created a version of llvm/clang for an architecture with some odd properties:
- front end side:
-- char,short,int : 20 bits
-- long, long long: 40 bits
-- pointer: 20 bits
On the backend side, I have hardware support for 20-bit registers (and load/stores).
(So, I have support for 'i20' and 'i40', but 'i40' is lowered into operations on 'i20')
2012 Jun 29
2
[LLVMdev] Comment "FIXME" in X86MachObjectWriter::RecordX86Relocation
Hi,
In X86MachObjectWriter::RecordX86Relocation I found the comment
if (Target.isAbsolute()) { // constant
// SymbolNum of 0 indicates the absolute section.
//
// FIXME: Currently, these are never generated (see code below). I
cannot
// find a case where they are actually emitted.
Type = macho::RIT_Vanilla;
}
Is the FIXME still true? I've got some code that
2012 Oct 19
0
[LLVMdev] Predication on SIMD architectures and LLVM
Hi Marcello,
On Fri, Oct 19, 2012 at 04:38:29PM +0100, Marcello Maggioni wrote:
> Hello,
> I'm working on a compiler based on LLVM for a SIMD architecture that
> supports instruction predication. We would like to implement branching
> on this architecture using predication.
> As you know the LLVM-IR doesn't support instruction predication, so I'm
> not exactly
2012 Jun 27
3
[LLVMdev] Counting instructions in MCJIT
Hi there,
I wondered whether anyone could give me any advice about counting
assembly instructions when using MCJIT?
For performance regression testing I would like to be able to count the
number of instructions generated during the jit compilation of a given
module.
The Statistic class, as far as I understand, cannot collect this data
per-module (per-ExecutionEngine/per-MCJIT), and there is
2012 Jun 29
0
[LLVMdev] Comment "FIXME" in X86MachObjectWriter::RecordX86Relocation
Hi Verena,
Windows + MachO is likely to run into lots of problems once you start passing in non-trivial code. The relocation model is very tied to Darwin.
I believe some folks doing JIT on Windows have had some success w/ ELF. Hopefully someone more familiar with the specifics of that will chime in.
-Jim
On Jun 29, 2012, at 8:58 AM, Verena Beckham <verena at codeplay.com> wrote:
>
2013 Apr 09
0
[LLVMdev] Getting the position of a BasicBlock that doesn't exist anymore in the backend
Hello,
In our LLVM backend we needto output certain labels in the AsmPrinter
in order to access certain data through those labels. These labels are
related to BlockAddress objects (that come from above) and they should
be put into a position that is related to the BasicBlock pointed by that
BlockAddress.
The problem I'm hitting is that if the BasicBlock that the BlockAddress
points to
2012 Jun 29
2
[LLVMdev] Comment "FIXME" in X86MachObjectWriter::RecordX86Relocation
Can I assume we're talking about MCJIT since a file format and relocations are involved?
Some changes are required in order to get MCJIT to generate ELF object files. Eli Bendersky submitted a patch some time ago to modify the target triple code to enable this, but after a bit of discussion there didn't seem to be a consensus for accepting this proposal.
If you want to try it out, the
2012 Jul 02
0
[LLVMdev] Comment "FIXME" in X86MachObjectWriter::RecordX86Relocation
Hi Jim, Andrew,
Thanks, I read the discussions about using ELF + MCJIT + Windows and was
hoping MachO would work just as well. Since you don't need to modify
LLVM to be able to output MachO this was my first choice.
But are you saying MachO will not work as well as ELF?
Thanks for the patch Andrew, that will have to be my plan B in this case.
Verena
On 29/06/2012 23:47, Kaylor, Andrew
2013 May 09
2
[LLVMdev] Scheduling with RAW hazards
I have an instruction that takes no operands, and produces two results,
in two consecutive cycles.
I tried both of the following to my Schedule.td file:
InstrItinData<IIMyInstr, [InstrStage<2, [FuncU]>], [1, 2]>,
InstrItinData<IIMyInstr, [InstrStage<1, [FuncU]>, InstrStage<1,
[FuncU]>], [1, 2]>,
From what I can see in examples, these say that the first
2012 Oct 19
0
[LLVMdev] Predication on SIMD architectures and LLVM
Hi Marcello,
I am sure I've seen some postings on the list concerning architectures
that support predicated execution and how to map that to LLVM IR, I'm
just not sure anymore when and who was involved :).
I have implemented your first suggestion for targets that do not have
predicated instructions (where control flow to data flow conversion with
explicit maintaining of masks and
2012 Oct 19
0
[LLVMdev] Predication on SIMD architectures and LLVM
Hi,
I've done work on predicated SIMD representations for LLVM.
If you search through the archives, you may find my "applymask" proposal,
which is an attempt at representing predication in a very comprehensive
way. I've since stopped pushing the proposal in part because Larrabee's
changing fortunes led to a decline of interest at the time, in part because
the proposal
2012 Jun 28
0
[LLVMdev] Counting instructions in MCJIT
Hi Verena,
I think that we can count the number of instructions with "-stats"
command line option. As you mentioned, this option uses Statistic class
like "STATISTIC(EmittedInsts, "Number of machine instrs printed");"
I don't know exactly about parallel code generation environment but
this option seems like to work correctly in common case as following.
This is
2013 Sep 27
1
[LLVMdev] TableGen and computed expressions
Thanks Elior,
Sorry for the delay - emergencies never seem to go away in compiler
development ;-)
That sounds like an interesting approach, a kind-of pre-processor for TD
files. But will this still not result in a constant, although externally
provided, or have I misunderstood?
What I would like to do is compute a different value depending on which
'-target-cpu <cpu>' option was
2014 Mar 03
2
[LLVMdev] Question about per-operand machine model
On Mar 3, 2014, at 8:53 AM, Pierre-Andre Saulais <pierre-andre at codeplay.com> wrote:
> Hi Andrew,
>
> We are currently using a custom model where scheduling information is attached to each MCInstrDesc through tablegen, and we're trying to move to one of LLVM's models.
>
> To expand on what JinGu mentioned, our target has explicit ports that are used to read and
2014 Mar 04
2
[LLVMdev] Question about per-operand machine model
On Mar 4, 2014, at 10:05 AM, Pete Cooper <peter_cooper at apple.com> wrote:
>
> On Mar 3, 2014, at 2:21 PM, Andrew Trick <atrick at apple.com> wrote:
>
>>
>> On Mar 3, 2014, at 8:53 AM, Pierre-Andre Saulais <pierre-andre at codeplay.com> wrote:
>>
>>> Hi Andrew,
>>>
>>> We are currently using a custom model where
2013 May 09
0
[LLVMdev] Scheduling with RAW hazards
On May 9, 2013, at 4:02 AM, Fraser Cormack <fraser at codeplay.com> wrote:
> I have an instruction that takes no operands, and produces two results, in two consecutive cycles.
>
> I tried both of the following to my Schedule.td file:
>
> InstrItinData<IIMyInstr, [InstrStage<2, [FuncU]>], [1, 2]>,
> InstrItinData<IIMyInstr, [InstrStage<1,