similar to: [LLVMdev] Reverse engineering for LLVM bit-code

LLVM IR represents higher level than assembler code, it keeps some names and it is easier to revert the IR to source code than a binary format. The main task of LLVM IR is code generation. I don't think adding obfuscation has particular worth, those who need it can use tools and approaches specifically aimed at obfuscation. Even simple rename of identifiers in source code makes C/C++ file

Hi, community: For the sake of our business need, I want to enable "Function-based parallel code generation" to boost up the compilation of single module, please see the details of the design and provide your feedbacks on below aspects, thanks! 1. Is this idea the proper solution for my requirement 2. This new feature will be enabled by llc -thd=N and has no impact on original llc when

While I think the end goal you're describing is close to the correct one, I see the high-level strategy for getting there somewhat differently: 1) The code generators are only one collection of function passes that might be parallelized. Many others might also be parallelized profitably. The design for parallelism within LLVM's pass management infrastructure should be sufficiently generic

-----Original Message----- From: Shuxin Yang [mailto:shuxin.llvm at gmail.com] Sent: Wednesday, July 17, 2013 1:50 AM To: Wan, Xiaofei Cc: Evan Cheng; Shuxin Yang; LLVM Developers Mailing List (llvmdev at cs.uiuc.edu) Subject: Re: [LLVMdev] [LLVM Dev] [Discussion] Function-based parallel LLVM backend code generation On 7/16/13 7:23 AM, Wan, Xiaofei wrote: > Yes, the purpose is similar, we

Hi, all: I am trying to test half float point support in llvm, I found clang can generate bitcode for __fp16, while llc can't generate code for it, the error message is like this LLVM ERROR: Cannot select: 0x26a68e0: i16 = fp32_to_fp16 0x26a67d8 [ORD=2] [ID=4] 0x26a67d8: f32,ch = CopyFromReg 0x2693060, 0x26a66d0 [ORD=2] [ID=3] 0x26a66d0: f32 = Register %vreg1 [ID=1] In function: test

Please see Shuxin's proposal on "parallelizing post-IPO stage". It seems the two projects are related. Evan On Jul 16, 2013, at 3:33 AM, "Wan, Xiaofei" <xiaofei.wan at intel.com> wrote: > Hi, community: > > For the sake of our business need, I want to enable "Function-based parallel code generation" to boost up the compilation of single module,

On Tue, Jul 16, 2013 at 3:33 AM, Wan, Xiaofei <xiaofei.wan at intel.com> wrote: > Hi, community: > > For the sake of our business need, I want to enable "Function-based parallel code generation" to boost up the compilation of single module, please see the details of the design and provide your feedbacks on below aspects, thanks! > 1. Is this idea the proper solution for

Yes, the purpose is similar, we started this job from last year; But it Shuxin's solution is module based (correct me if I am wrong), we tried this solution and failed for many reasons, it is described in my design document https://docs.google.com/document/d/1QSkP6AumMCAVpgzwympD5pI3btPJt4SRgjY-vhyfySg/edit?usp=sharing we need discuss two solution and compare them, then adopt one solution

On 7/16/13 7:23 AM, Wan, Xiaofei wrote: > Yes, the purpose is similar, we started this job from last year; > But it Shuxin's solution is module based (correct me if I am wrong), we tried this solution and failed for many reasons, it is described in my design document > https://docs.google.com/document/d/1QSkP6AumMCAVpgzwympD5pI3btPJt4SRgjY-vhyfySg/edit?usp=sharing > > we need

On 7/16/2013 9:51 PM, Wan, Xiaofei wrote: > [Xiaofei] why? I don't understand it very well here, you mean it can > generate totally identical binaries as the original llc, including the > function order (function order may not affect code quality, but we > should make sure the output is same in each run)? Per <http://www-plan.cs.colorado.edu/diwan/asplos09.pdf>, function

Hello, This patch aims to improve compile time performance by increasing the SCEV vector size in LoopStrengthReduce. It is observed that the BaseRegs vector size is 4 in most cases, and elements are frequently copied when it is initialized as SmallVector<const SCEV *, 2> BaseRegs. Our benchmark results show that the compilation time performance improved by ~0.5%. Patch by Wan Xiaofei.

I have a http proxy across tinc linked remote networks. It works generally well, but few times a day it gives a timeout, which disconnects some more sensitive clients. It is nginx based and setting longer timeouts, disabling or extending buffers did not help. Do you have any experience with a tinc or lower level networking parameters which could be used to mitigate such an annoying behaviour?

The next LLVM social in Paris will happen on January 30th, 2018. Everyone interested in LLVM, Clang, lldb, Polly, lld, ... is invited to join. Event details, including registration (free but mandatory) at http://www.meetup.com/LLVM-Clang-social For this meetup, Adrien Guinet, Serge Guelton and Juan Manuel Martinez will talk about the "Challenges when building an LLVM bitcode

I just made a rails application that I plan to sell and dsitribute. I want to distribute it without having to worry about someone stealing the code and selling their own version. How do I do this? Is there a ruby obfuscator or anything that can keep someone from seeing the code? Thanks for your help. -- Posted via http://www.ruby-forum.com/.

Hi all mailing listers, I wanna get the last several elments of vector. e.g. x <- c(1,2,3,.....,78, 79, 80) How can I implement to assign last three elements to y, y <- c(78, 79, 80) ? In Matlab, It can easily achieve by y=x(end-2:end) Thanks Huaping Wan [[alternative HTML version deleted]]

Hi Andrea    Thank you your replying.    I do like your letter. Add following to line to MipsISelLowering.cpp. As your words,   @llvm.convert.to.fp16  can compile successfully. However, the runtime is not right. +  setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);+  setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand); Robin yalong at multicorewareinc.com  From: Andrea Di

Hello everybody! I am a Linux admin trying to move my mail system based on qmail to the software which is more spam-protected: exim4 + dovecot-1.0rc15 + pgsql . I've downloaded and rebuild dovecot from src.rpm (for fc4). During the testing stage I've discovered two troubles: 1) the problem with deliver (...I'm not sure it's a really bug). Here is relevant part of my

I''ve just created a rails application for a friend''s business. I''m going to place the application onto one of his computers so he can access it from within his network. What can i do to make sure he cannot read/edit the code? I can''t see what i can do. Its on a windows xp machine and he has full admin rights. He''s not an expert PC user so the solution

Hello After add some packagelist to puppet class. I get lots of warning message "appears to have a negative number of dependencies". My puppet master and agent version are 3.3.1. Here is the log out: [root@gpu022 ~]# puppet agent --test Info: Retrieving plugin Info: Loading facts in /var/lib/puppet/lib/facter/puppet_vardir.rb Info: Loading facts in

I'm wondering why the lit tests didn't catch this as part of testing rc1 on ARM. On Thu, Jan 26, 2017 at 11:25 AM, Serge Rogatch <serge.rogatch at gmail.com> wrote: > XRay is tested automatically on build-bots with tests in LLVM and > compiler-rt . Or are you asking for manual testing instructions? > Of these 2 patches, the compiler-rt patch depends on LLVM patch because