Displaying 20 results from an estimated 2000 matches similar to: "[LLVMdev] llvm jit"
2013 Oct 07
1
[LLVMdev] llvm jit
hello,
I have a question about the llvm jit.
Does it use the profile information generated during runtime to enhance the
generated code for arm processor?
according to 'LLVM: A Compilation Framework for Lifelong Program
Analysis **<http://llvm.org/pubs/2004-01-30-CGO-LLVM.html>'
it is available but can't find it in the current source code.
I really appreciate any help.
Thanks in
2013 Nov 03
0
[LLVMdev] loop vectorizer issue
Hi Sarah,
the loop vectorizer runs not on the C code but on LLVM IR this c code was lowered to. Before the loop vectorizer runs many other optimization change the shape of this IR.
You can see in the LLVM IR you referenced below, a preceding LLVM IR transformation has change your loop from:
> for(int k=20;k<50;k++)
> dataY[k] = dataY[k-1];
to
> int a = d[19];
>
2013 Nov 03
3
[LLVMdev] loop vectorizer issue
Actually what I meant in my original loop, that there is a dependency
between every two consecutive iterations. So, how the loop vectorizer says
'we can vectorize this loop'?
for(int k=20;k<50;k++)
dataY[k] = dataY[k-1];
From: Henrique Santos [mailto:henrique.nazare.santos at gmail.com]
Sent: Sunday, November 03, 2013 4:28 PM
To: Sara Elshobaky
Cc: <llvmdev at
2013 Nov 03
0
[LLVMdev] loop vectorizer issue
Notice that the code you provided, for globals and stack allocations, at
least,
is semantically equivalent to:
int a = d[19];
for(int k = 20; k < 50; k++)
dataY[k] = a;
Like so, the load you see missing was redundant, probably hoisted by
GVN/PRE
and replaced with "%.pre".
H.
On Sun, Nov 3, 2013 at 11:26 AM, Sara Elshobaky <sara.elshobaky at gmail.com>wrote:
>
2013 Nov 03
2
[LLVMdev] loop vectorizer issue
Hello,
I was trying to trace the Loop vectorizer of the LLVM, I wrote a simple loop
with a clear dependency.
But found that the debug shows that 'we can vectorize this loop'
Here you are my loop with dependency:
for(int k=20;k<50;k++)
dataY[k] = dataY[k-1];
And the debug prints:
LV: Checking a loop in "main"
LV: Found a loop: for.body4
LV: Found an
2014 Sep 01
2
[LLVMdev] Modify a module at runtime in MCJIT
Hello,
I'm using MCJIT to run some loops on my ARM processor.
I was trying to perform some runtime optimizations on some function, and
this requires recompiling the function at runtime.
I know that this feature is not available yet in MCJIT , and to modify a
function I have to create a new module with the newly optimized code.
My questions are:
- The newly created module can be
2013 Oct 04
1
[LLVMdev] Runtime optimizer
Hello,
Please, I need more information on the runtime optimizer used in the LLVM
JIT.
- Where can I find it in the LLVM source code?
- Are those runtime optimizations done on the LLVM representation
code or on the machine code?
Sara
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2014 Jan 26
3
[LLVMdev] Number of instructions executed
Hello,
I'm executing my byte code program by the lli tool using mcjit.
I need a way to find statistics about the number of instructions executed
for my program.
The -stats option does not include this value, are there any other way to
know?
I need this information to compare different versions of my bytecode
program.
Please advice
Thanks in advance
Sara Elsohbaky
--------------
2014 Feb 25
2
[LLVMdev] noinline attribute problem
Hello,
I have the following simple C code below. It should return '8' as a result.
But the returned result is false as it returns '1'.
When I remove the line of '__attribute__((noinline))' , the returned results
are correct '8'.
Any idea? Please advice as I need to get the assembly code of the
'getTexSize' function alone.
Note: I compile using the
2013 Apr 14
2
[LLVMdev] Citing LLVM
In the past, I've just referenced Chris's CGO 2004 paper when referring to
LLVM:
C. Lattner and V. Adve. LLVM: A compilation framework for lifelong program
analysis & transformation.
For sub-projects like Clang and DragonEgg, I just cite the URLs:
[4] Clang. clang.llvm.org.
[5] DragonEgg. dragonegg.llvm.org.
I don't know of any canonical references for these.
On Sun, Apr 14,
2013 Apr 15
0
[LLVMdev] Citing LLVM
On 4/14/13 3:35 PM, Justin Holewinski wrote:
> In the past, I've just referenced Chris's CGO 2004 paper when
> referring to LLVM:
I second that. We at Illinois typically cite Chris's CGO paper. The
bibtex is:
@InProceedings{LLVM:CGO04,
Author = {Chris Lattner and Vikram Adve},
Title = {{LLVM}: A Compilation Framework for Lifelong Program
Analysis and
2013 Sep 04
1
[LLVMdev] opengl es 2
Hello,
Can LLVM execute OpenGL ES 2.0 programs safely?
As I tried a simple code, and I get some crashes while using lli
example
LLVM ERROR: Program used external function '__dso_handle' which could not be resolved!
Thanks in advance
Sara
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2013 Nov 23
1
[LLVMdev] prevents instruction-scheduler from interfereing instruction pair
I think this after a second. I got your point. I can define a pseudo
instruction for an instr-pair and expand it after post-RA-sched. as you
said, in preEmitPass.
The original intrinsic can also be kept. I just convert the intrinsic to
pseudo instruction in TargetLower. Thank you for your enlightening
suggestion!
thanks,
--lx
On Sat, Nov 23, 2013 at 8:37 PM, Amara Emerson <amara.emerson at
2017 Feb 10
2
RFC: Generic IR reductions
On 9 February 2017 at 17:31, Amara Emerson <amara.emerson at gmail.com> wrote:
> Ping. Does anyone else have thoughts on this?
Hi Amara,
It seems the people who replied in this thread are mostly in sync with
the proposal, why don't you push a review in phab, and let's take this
to the next level?
cheers,
--renato
2013 Nov 23
2
[LLVMdev] prevents instruction-scheduler from interfereing instruction pair
Amara,
first, thank you for answering. but I found expandPsuedo instructions
actually happens before post-RA, like the following code showing:
your approach is a little hacky, right? : )
// Expand pseudo instructions before second scheduling pass.
addPass(&ExpandPostRAPseudosID);
printAndVerify("After ExpandPostRAPseudos");
// Run pre-sched2 passes.
if (addPreSched2())
2013 Nov 23
0
[LLVMdev] prevents instruction-scheduler from interfereing instruction pair
What I meant was to write your own expansion pass and run it after the
scheduler passes, e.g. in the pre-emit stage.
> if (addPreEmitPass())
printAndVerify("After PreEmit passes")
Though if it's too hacky for you then fair enough.
Amara
On 23 November 2013 03:17, Liu Xin <navy.xliu at gmail.com> wrote:
> Amara,
>
> first, thank you for answering. but I found
2017 Feb 03
2
RFC: Generic IR reductions
Yes, SVE can vectorize early exit loops by using speculative
(first-faulting) loads, which essentially give a predicate of the
lanes loaded successfully. For uncounted loops with these special
loads, the loop predicate tests can be done using a 'ptest'
instruction, checking if the last element is active.
Amara
On 3 February 2017 at 10:15, Simon Pilgrim <llvm-dev at redking.me.uk>
2018 Jan 02
0
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Unless there are still open issues with your patch, or our internal bots point to problems, I think time has come to flip the switch.
Thanks
Gerolf
> On Dec 18, 2017, at 11:14 AM, Amara Emerson via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
> FYI all: the patch to enable it is available to review here: https://reviews.llvm.org/D41362 <https://reviews.llvm.org/D41362>
2017 Dec 18
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
FYI all: the patch to enable it is available to review here: https://reviews.llvm.org/D41362
Thanks,
Amara
> On Dec 18, 2017, at 5:44 PM, Amara Emerson via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
> Ok. We’ll look at what we can do to further stress test it in the next two months, additional suggestions from the community is welcome. Patch should be incoming to enable it
2014 Jun 23
2
[LLVMdev] VFP3
I am not using llvm tools, but sources and directly calling into relevant
LLVM classes and methods.
Thanks,
Daman
On 23/06/14 4:11 pm, "Amara Emerson" <amara.emerson at gmail.com> wrote:
>Hi Damanjit,
>
>I assume you're trying to use the tools like llvm-mc, in which case
>you can use the -mattr=+vfpv3 flag to enable it. This applies to other
>subtarget