similar to: [LLVMdev] Help with a Microblaze code generation problem.

Hi, i'm working on a microblaze port extremely similar to microblaze that only has data hazards. The advice given to look at PPC and ARM is poor because neither of them check for data dependencies and are entirely complicated and different. The port has a 5 stage pipeline where the result of instruction can only be used at stage 3 and 5 only whereas load and store instructions require 4

The Sparc, Microblaze, and Mips code generators implement branch delay slots. They all seem to exhibit the same bug, which is not surprising since the code is very similar. If I compile code with this snippit: while (n--) *s++ = (char) c; I get this (for the Microblaze): swi r19, r1, 0 add r3, r0, r0 cmp r3, r3, r7 beqid r3,

Hi, we have seen proper register numbers when we have generated assembly files through clang but when we generated dump files from object file then we didn't see expected register numbers. Note : all registers are replaced with R0 *Disassembly of section .text:00000000 <main>: 0: 3000ffcc addik r0, r0, -52 4: f8000000 swi r0, r0, 0 8:

Hello All, I was trying to add Microblaze target to LLVM backend. I was able to generate object file with relocations. and debug symbols. When I try to link this object file with microblaze GCC linker I am getting below errors and debug symbols are missing in it. mb-objdump: DWARF error: found dwarf version '15877', this reader only handles version 2, 3, 4 and 5 information

On Saturday, April 18, 2020, David Blaikie <dblaikie at gmail.com> wrote: > > > On Sat, Apr 18, 2020 at 3:02 AM Nagaraju Mekala via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> Hello All, >> >> I was trying to add Microblaze target to LLVM backend. I was able to >> generate object file with relocations. and debug symbols. >>

On Sat, Apr 18, 2020 at 11:11 PM David Blaikie <dblaikie at gmail.com> wrote: > > Yeah, not sure - you mention the linker produces errors, but the errors you showed looked like objdump errors? Were those errors from trying to dump the linked executable, and not errors that were produced by the linker itself? Yes, as mentioned earlier I was able to generate final executable but it

Hello, this is a very dump question, I hope to do more valuable question soon, but for now I'm just trying to run a simple hello world in C for clang and llvm to the target mblaze, but is not working. ( I need to change the compiler in the next stage) I past all the weekend tried to run this, and I was unable, I did the build of llVM/clang, but no bin was generate, only silly folder that I

Hi James, Thanks for reply. When I looked in to the generated debug dump from the object file I found that DW_AT_name is always (indirect string, offset: 0x0): clang version 8.0.1, instead of variable names. Below is a sample output of the debug dump. Compilation Unit @ offset 0x0: Length: 0x6a (32-bit) Version: 4 Abbrev Offset: 0x0 Pointer Size: 4

I didn't have Mips board. I compile as the commands and check the asm output as below. 1. Question: The distance of caller arg[4] and arg[5] is 4 bytes. But the the callee get every arg[] by 8 bytes offset (arg_ptr1+8 or arg_ptr2+8). I assume the #BB#4 and #BB#5 are the arg_ptr which is the pointer to access the stack arguments. 2. Question: Stack memory 28($sp) has no initial value. If

Does it make a difference if you give the "-target" option to clang? $ clang -target mips-linux-gnu ch8_3.cpp -o ch8_3.bc -emit-llvm -c The .s file generated this way looks quite different from the one in your email. On Tue, Feb 19, 2013 at 5:06 PM, Jonathan <gamma_chen at yahoo.com.tw> wrote: > I didn't have Mips board. I compile as the commands and check the asm >

Hi, how can i get work Samba 4 Sernet 4.1.7 correctly with NIS. Ist provisioned with rfc2307. When i query a User withi get the following. getent passwd testswi SWI\testswi:*:10000:100:testswi:/home/SWI/testswi:/bin/false I want to change /bin/false to a other value /bin/bash I tried many things to change the value. 1. ldbedit -e vim -H /var/lib/samba/private/sam.ldb samaccountname=testswi

Hi, General Question. Anybody should answer this. Which files are really hard links and which not? from /var/lib/samba/private/sam.ldb.d/ --> /var/lib/samba/private/sam.ldb.d/ 2872186 -rw-rw---- 1 root named 7675904 Sep 8 22:04 CN=CONFIGURATION,DC=SWI,DC=LOCAL.ldb <-? 2872187 -rw-rw---- 1 root named 9359360 Sep 8 22:04 CN=SCHEMA,CN=CONFIGURATION,DC=SWI,DC=LOCAL.ldb <-? 2872184

Which part of the generated code do you think is not correct? Could you be more specific? I compiled this program with clang and ran it on a mips board. It returns the expected result (21). On Tue, Feb 19, 2013 at 4:15 AM, Jonathan <gamma_chen at yahoo.com.tw> wrote: > I check the Mips backend for the following C code fragment compile result. > It seems not correct. Is it my

I check the Mips backend for the following C code fragment compile result. It seems not correct. Is it my misunderstand or it's a bug. //ch8_3.cpp #include <stdarg.h> int sum_i(int amount, ...) { int i = 0; int val = 0; int sum = 0; va_list vl; va_start(vl, amount); for (i = 0; i < amount; i++) { val = va_arg(vl, int); sum += val; } va_end(vl);

Jeff thanks for those suggestions, that's exactly what i would like to do, however i dont know how to do it with my current knowledge :\ As far as i understand patterns only take one instruction as an input (while the pattern you wrote before takes two) and also, i dont know how to handle register copying (COPY) in the .td file because they're handled in a different way to the rest of

Hi everyone I'm fairly new with LLVM and I've been searching around but couldn't find info on this subject. I started working on a target for a new cpu and I realizing my initial simple understanding of instruction itineraries may be completely off. I'm trying to model a CPU that has a latency of 2 cycles for multiplications fully pipelined (so it can start a new one after one

Implement "pid_t vfork(void)" for parisc. Signed-off-by: Kyle McMartin <kyle at parisc-linux.org> --- Ugh. vfork() me harder. Kbuild | 2 +- vfork.S | 31 +++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/usr/klibc/arch/parisc/Kbuild b/usr/klibc/arch/parisc/Kbuild index d57a873..57ca5c2 100644 --- a/usr/klibc/arch/parisc/Kbuild

On Nov 27, 2010, at 8:56 AM, Borja Ferrer wrote: > Some background first: this issue is for a backend for an 8bit microcontroller with only 8bit regs, however it has a few 16bit instructions that only work with fixed register pairs, so it doesnt allow all combinations of regs. This introduces some problems because if data wider than 8bits is expanded into 8bit operations the 16bit instructions

On Mon, Aug 15, 2011 at 4:03 PM, Miguel G <miguel at esenciatech.com> wrote: > Hi everyone > I'm fairly new with LLVM and I've been searching around but couldn't find > info on this subject. > I started working on a target for a new cpu and I realizing my initial > simple understanding of instruction itineraries may be completely off. > I'm trying to model a

Hello, some months ago i wrote to the mailing list asking some questions about register pairing, i've been experimenting several things with the help i got back then. Some background first: this issue is for a backend for an 8bit microcontroller with only 8bit regs, however it has a few 16bit instructions that only work with fixed register pairs, so it doesnt allow all combinations of regs.