Displaying 20 results from an estimated 40000 matches similar to: "[LLVMdev] Some reflexions about a new HDL language"
2013 Aug 30
2
[LLVMdev] Reflexions about a new HDL language
Hello,
I previously sent this message, but it was in HTML only, so it was
unreadable.
I am thinking about making a compiler for a new HDL language, that will
be more modern than VHDL and Verilog and allow a little higher level
behavioral description than VHDL. For this language, I am beeing
influenced by VHDL, Ada, Ruby and MyHDL. I also would like to write it
in Ada.
I don't know if it
2013 Aug 30
0
[LLVMdev] Reflexions about a new HDL language
If you're designing a new high-level HDL, then it would be a good idea to familiarise yourself with the state of the art in this area (e.g. Bluespec System Verilog, Symbolics Processor Designer, and similar tools). Starting from comparisons to VHDL and Verilog is like designing a new high-level programming language today that is designed to be a better high-level programming language that is
2013 Aug 30
4
[LLVMdev] Reflexions about a new HDL language
Hi,
For the synthesis backend which translate to VHDL or Verilog, I don't
know if I will use LLVM. It will depend on how easy it is to play with
concurrent statements with LLVM. For the simulation I will use LLVM
because I can anyways artificially make the compiled code sequencial. It
would allow me to benefit from all the nice things from LLVM like
existing optimisations. I have never
2013 Aug 30
0
[LLVMdev] Reflexions about a new HDL language
Jonas Baggett <jonasb at tranquille.ch> writes:
> What are your feedbacks ?
Hello Jonas,
How is that related to LLVM? I see no references to LLVM on your
announcement nor on your document.
2013 Aug 30
0
[LLVMdev] Some reflexions about a new HDL language
2013 Sep 18
1
[LLVMdev] Reflexions about a new HDL language
Le 30. 08. 13 11:59, David Chisnall a écrit :
> If you're designing a new high-level HDL, then it would be a good idea to familiarise yourself with the state of the art in this area (e.g. Bluespec System Verilog, Symbolics Processor Designer, and similar tools).
That's a good idea before I go too far , and I think that MyHDL worths a
look too. For Symbolics Processor Designer, I tried
2008 Jul 03
3
Active-HDL
Hey!
I was wondering if active-HDL (VHDL simulator) will work with WINE 1.0?
active-HDL (i regret to say) is only for windows.... :(
Thanks :)
2007 Aug 28
1
HDL F10 brazilian doorbell device + TDM2400
Hi,
I'm trying to connect an HDL F10 device for a friend living in Brazil to
the TDM2400 on his Asterisk server.
That device should behave like a normal doorbell and it is if connected
to an analog PBX.
I connected to the TDM2400 and everything works fine except for one
thing: when the called party hangs up his phone, the F10 HDL device does
not hang up.
I'm not brazilian and not
2008 Dec 08
0
sndio support for libao
(Is this the right list for libao patches?)
The following adds support for a sndio plugin to libao. sndio is
OpenBSD's new audio API.
diff -uNrp libao-0.8.8.orig/configure.ac libao-0.8.8/configure.ac
--- libao-0.8.8.orig/configure.ac Thu May 24 12:51:05 2007
+++ libao-0.8.8/configure.ac Mon Dec 8 16:34:44 2008
@@ -300,6 +300,11 @@ dnl Check for Sun audio
AC_CHECK_HEADERS(sys/audioio.h)
2013 May 06
3
[LLVMdev] Do we abuse the "nsw" flag
Hi, There:
Clang fails to compile 254.gap @ CPU2000int suite. The symptom is
that executable fail to run
with reference input.
The root cause is that the compiler mistakenly optimizes expr "x * y
/ y" into x where the x*y is blindly
flagged with nsw without any analysis.
The preproceeded code is excerpted bellow:
cat -n integer.i
---------------------------------
2361
2013 May 06
0
[LLVMdev] Do we abuse the "nsw" flag
This has come up before, and we just added -fwrapv to work around the problem:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20110131/115969.html
Are you compiling without -fwrapv?
Cameron
On May 6, 2013, at 4:55 PM, Shuxin Yang <shuxin.llvm at gmail.com> wrote:
> Hi, There:
>
> Clang fails to compile 254.gap @ CPU2000int suite. The symptom is that executable
2005 Oct 17
0
Ordinal GEE model
Hi,
I am trying to fit a ordinal GEE model using ordgee {geepack}. In order to check the validity of the function, I specified the correlation structure as independence (i.e. constr = "independence") and compared the result with that using polr {MASS}.
Because a GEE model with an independent working correlation structure is equivalent to an ordinary GLM model, we would expect the same
2008 Jan 16
1
Probability weights with density estimation
I am a physician examining an NHANES dataset available at the NCHS
website:
http://www.cdc.gov/nchs/about/major/nhanes/nhanes2005-2006/demo_d.xpt
http://www.cdc.gov/nchs/about/major/nhanes/nhanes2005-2006/hdl_d.xpt
http://www.cdc.gov/nchs/about/major/nhanes/nhanes2005-2006/tchol_d.xpt
Thank you to the R authors and the foreign package authors in
particular. Importing from the SAS export
2009 Jul 17
2
Fisher's exact test
Hi,
I'm trying to run Fisher's Exact test on the data below, but I'm not
sure how interpret the data shown. Can someone tell me what this is
saying? Looking at the numbers it should be that there's no significant
difference between the HDL and LDL, but a p-value of 1 seems high. Is
the low value in the LDL unbound making the test unstable and should I
be using an alternative?
Best
2018 Apr 27
1
Introducing HardCloud @ FCCM 2018
Hi,
HardCloud (www.hardcloud.org) is an extension to the OpenMP 4.X standard
that seeks to ease the task of offloading IP-cores to FPGA accelerators in
CPU-FPGA architectures. This is achieved by two new clauses [use] and
[module] shown in the example below:
#pragma omp target device(HARP | HARPSIM | Catapult) map(to: X) map(from: Y)
#pragma omp parallel for use(hrw) module(loopback) check
2012 Jun 09
1
combining different types of graphics (scatterplots, boxplots) using lattice
Dear R users:
I have a continuous outcome variable and four predictors, two continuous and
two dichotomous. i would like to use the lattice plot to create scatter
plots for the continuous predictors and boxplots for the dichotomous
predictors.
with 4 continuous variables, this is what i have been doing:
trial = rbind (
cbind ( cimt$ant.mean, cimt$age, 1 ),
cbind ( cimt$ant.mean, cimt$sbp, 2 ),
2011 Oct 02
7
[LLVMdev] LLVM and VHDL simulation
Hi,
I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process.
To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis is not a list of assembly instructions but a description of a circuit with logical gates. This
2016 Jul 21
2
RFC: LLVM Coroutine Representation, Round 2
cc llvm-dev
On Thu, Jul 21, 2016 at 9:57 AM, Vadim Chugunov <vadimcn at gmail.com> wrote:
> Hi Gor,
> Does you design support resumption with parameter(s)? (such as Python's
> generator.send(x)). I suppose the "promise" could be used for passing data
> both ways, but if that's the plan, please mention this explicitly in the
> design doc.
> Also, how is
2007 Jul 24
0
[LLVMdev] LLVM Expansions
It is very relevant that LLVM look into handeling HDL and other binary
and analogue operation modeling capbilities, as well as expand this
abstractly above in the other direction to include complex structure
optimization that is critical in realtime, dynamic and VM operations.
Without confirming the true characteristics of the lower structure
types and operating characteristics (especially
2004 Aug 16
2
randomize Dial() target
Hi,
is it possible to randomize extension which would be choosed by Dial()?
I would like to forward phone calls to one of sales rep in randomized
way (not to harm anyone;) ).
tia
mazek
--
http://www.marcinmazurek.com/ ::: nic-hdl: MM3380-RIPE
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