similar to: [LLVMdev] Maintaining LiveIn

The unchecked assertion that the same register is not added multiple times to the MBB::LiveIn list isn't being respected. Could we add an assertion to check for it? ==== //dwarc/Tools/MetaWare/Toolset/main/dev/llvm/include/llvm/CodeGen/MachineBasicBlock.h#6 - /remote/arctools/marksl/marksl_1/llvm/include/llvm/CodeGen/MachineBasicBlock.h ==== 295,298d294 < /// addLiveIn - Add the

Hi all, Is there a pass that computes livein information for each MachineBasicBlock? I tried to find such a pass but could not find any. I am trying to use the livein information to get dead registers to insert some instructions right before code emission but the livein information seems to be invalidated by some pass. I might need to recompute the livein information before my pass. Thanks a

Hi Tom, As far as I can tell EmitLiveInCopies is just there to handle physreg arguments and return values. Is there any reason for these to change late in your backend? - Lang. On Tue, Feb 14, 2012 at 7:22 AM, Tom Stellard <thomas.stellard at amd.com>wrote: > On Mon, Feb 13, 2012 at 10:17:11PM -0800, Lang Hames wrote: > > Hi Tom, > > > > I'm pretty sure this

Hi Tom, I'm pretty sure this function should only ever be called once, by SelectionDAG. Do you know where the second call is coming from in your code? Cheers, Lang. On Mon, Feb 13, 2012 at 7:03 PM, Stellard, Thomas <Tom.Stellard at amd.com>wrote: > This patch seems to have been lost on the llvm-commits mailing list. > Would someone be able to review it? > > Thanks, >

This patch seems to have been lost on the llvm-commits mailing list. Would someone be able to review it? Thanks, Tom ________________________________________ From: llvm-commits-bounces at cs.uiuc.edu [llvm-commits-bounces at cs.uiuc.edu] on behalf of Tom Stellard [thomas.stellard at amd.com] Sent: Friday, February 03, 2012 1:55 PM To: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits]

On Mon, Feb 13, 2012 at 10:17:11PM -0800, Lang Hames wrote: > Hi Tom, > > I'm pretty sure this function should only ever be called once, by > SelectionDAG. Do you know where the second call is coming from in your code? > > Cheers, > Lang. Hi Lang, I was calling EmitLiveInCopies() from one of my backend specific passes. If the function can only be called once, then

I think what's happening is BranchFolder::MaintainLiveIns is using a forward analysis on top of these missing kill flags, and updating the BB-live-ins/live-outs with an incorrect set of registers. Then when the stackmaps liveness analysis happens, it's not doing anything wrong, but it starts with the wrong set of live registers and will propagate those to the point of the

On 4/16/13 11:30 AM, dag at cray.com wrote: > Is there a traditional dataflow algorithm buried in LLVM somewhere? I > need to be able to do some very late transformations (after regalloc) > and we aren't in SSA anymore. I will need a dataflow analysis to ensure > correctness. > > At one point I thought I remembered seeing a generic fixed-point > dataflow analysis engine

Is there a traditional dataflow algorithm buried in LLVM somewhere? I need to be able to do some very late transformations (after regalloc) and we aren't in SSA anymore. I will need a dataflow analysis to ensure correctness. At one point I thought I remembered seeing a generic fixed-point dataflow analysis engine but now I can't find it. Does it still exist or did it ever exist? If

On Apr 16, 2013, at 10:27 AM, John Criswell <criswell at illinois.edu> wrote: > On 4/16/13 11:30 AM, dag at cray.com wrote: >> Is there a traditional dataflow algorithm buried in LLVM somewhere? I >> need to be able to do some very late transformations (after regalloc) >> and we aren't in SSA anymore. I will need a dataflow analysis to ensure >> correctness.

Adds code to have DCE start off with a list of physical registers to be live on entry to at least one successor basic block (as mentioned in the FIXME comment). -- Sanjoy Das http://playingwithpointers.com -------------- next part -------------- A non-text attachment was scrubbed... Name: FIXME.patch Type: text/x-diff Size: 899 bytes Desc: not available URL:

On Jun 21, 2011, at 12:51 AM, Sanjoy Das wrote: > Adds code to have DCE start off with a list of physical registers to be > live on entry to at least one successor basic block (as mentioned in the > FIXME comment). Looks good, but keep the comment (sans FIXME).

The comment in test/CodeGen/X86/branchfolding-undef.mir states that such merging is legal, however doing so can actually generate wrong code: Consider this (valid code): --- name: fred tracksRegLiveness: true body: | bb.0: successors: %bb.1, %bb.2 J2_jumpt undef %p0, %bb.2, implicit-def %pc J2_jump %bb.1, implicit-def %pc bb.1: successors: %bb.3 %r0 =

Hi Jacob, At this point, I suspect there is a problem with maintaining liveness information during branch folding. Here is what I see: I have a basic block ready for branch optimization, that computes a predicate p10 on which a conditional branch depends. Notice that this is in the stage with physical registers. BB#2: derived from LLVM BB %while.cond.preheader Live Ins: %R3 %R5

While migrating my codebase from llvm-2.6 to llvm-2.7, I found a different behaviour in the register allocation. I have been able to reproduce it using the msp430 backend, with the 2.7 release as well as the svn head. For the msp430, the first four parameters of a function are passed thru registers. What I observe is that if those parameters are not used inside the function, those registers can

On Jun 14, 2011, at 1:07 AM, Duncan Sands wrote: > Hi Andrew, > >> No. Duncan suggested that he could hitch a ride with us through France. The problem is, we're not driving to Spain at all and there doesn't appear to be any place to transfer. >> >> The point is, you're not going to be able to leverage most of a CFG-based optimizing compiler if don't use

On Mar 25, 2007, at 7:12 AM, Christopher Lamb wrote: > While beginning to add vector registers to a back end I came across > the following problem: as soon as I define two sets of registers > that have a many-to-one mapping the live interval pass appears to > double-kill the mapped-onto register. I have the following excerpts > from my RegisterInfo.td. > > def V4R0

I've ran across an issue in BranchFolding.cpp where it is incorrectly folding a branch to the wrong fallthrough location. This is in LLVM 2.4 and seems to be in 2.5 also. The code in question is: void BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) { MachineFunction::iterator FallThrough = MBB; ++FallThrough; // If this block is empty, make everyone use its fall-through, not

Hi, I have a compiler project using an LLVM backend (compiled for 64 bit windows), and since it has started to get to production level source code sizes the compile times have gotten somewhat extreme (around 30 mins each time). Not sure what is the best metric for measuring whether 30 mins is reasonable. The .ll output file is ~1.5 million lines. A snip of the top of the stats output is

I'm having trouble with overlapping intervals for vector registers. How are intervals for registers that both alias to the same larger register intended to be handled? To demonstrate this problem you can use a minor addition to the Sparc register description. Add this to the SparcRegisterInfo.td at line 68: // Rtest class Rtest<bits<5> num, string n, list<Register>