similar to: [LLVMdev] Vector DAG Patterns

To elaborate, it is not only cumbersome writing these patterns for vectors of 16 characters (v16i8), it does not work. When I compile with this pattern for an andx operation on v16i8: /[(set RC:$dst,// // (and (i8 (vector_extract(vt VC:$src), 0 ) ), // // (and (i8 (vector_extract(vt VC:$src), 1 ) ),// // (and (i8 (vector_extract(vt VC:$src), 2 ) ),// ////(and (i8 (vector_extract(vt

Hi Rail, We used a very simple pattern expansion (actually, not a pattern fragment). For example, for AND, ADD (horizontal sum), OR and XOR of 4 elements we use something like the following TableGen structure: class HORIZ_Op4<SDNode opc, RegisterClass regVT, ValueType rt, ValueType vt, string asmstr> : SHAVE_Instr<(outs regVT:$dst), (ins VRF128:$src),

On Sep 24, 2008, at 9:15 AM, David Greene wrote: > >> 1. Treat these instructions as cross register class copies. The src >> and dst classes are different (VR128 and FR32) but "compatible". > > This seems reasonable. > >> 2. Model it as extract_subreg which coalescer can eliminate. >> >> #2 is conceptually correct. The problem is 128 bit XMM0 is

Tracking down a problem with one of our benchmark codes, we've discovered that some of the patterns in X86InstrX86-64.td are wrong. Specifically: def MOV64toPQIrm : RPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), "mov{d|q}\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (v2i64 (scalar_to_vector

This would be really cool. We have several instructions that perform horizontal vector operations, and have to use built-ins to select them as there is no easy way of expressing them in a TD file. Some like SUM for a ‘v4i32’ are easy enough to express with a pattern fragment, SUM ‘v8i16’ takes TableGen a long time to compute, but SUM ‘v16i8’ resulted in TableGen disappearing into itself for

Hi All, I'm working on a back end for an architecture that makes use of multi- typed register classes. def MR: RegisterClass<"namespace", [type1, type2, ... ], ... > When running some preliminary tests I found that the instruction selector refused to select certain ops (specifically stores) for some instructions when the operand type wasn't the first type for the

Hello, I am trying to create a machine instruction for "extractelement". I want to translate r <- extractelement v, 0 to mov r, v.x I was looking at the dag I can use and I found vector_extract. The inputs for this SDnode are a register and a iPtr constant. With that, I need to create 4 separate def's to extract element 0, 1, 2, and 3 and translate to v.x, v.y, v.z, and v.w. I

On Wed, September 24, 2008 12:10 am, Evan Cheng wrote: > > On Sep 23, 2008, at 7:17 PM, David Greene wrote: > >> Chris Lattner wrote: >>> On Sep 23, 2008, at 11:26 AM, David Greene wrote: >>> >>>> Are there any examples of using tablegen to generate multiple >>>> machine >>>> instructions from a single pattern? Or do these cases

On Feb 12, 2007, at 1:41 AM, Christopher Lamb wrote: > > selector refused to select certain ops (specifically stores) for some > instructions when the operand type wasn't the first type for the > register class. After some digging around I seem to have solved the > problem by creating bitconvert patterns between the types in the > register class like the following: > >

On Tuesday 24 November 2009 14:12, Anton Korobeynikov wrote: > Hello, David > > > How does ${dst:subreg32} work? > > This is just modifier provided to asmprinting code. Here, it seems, 16 > bit register is passed to asmprinter, but it sees modifier and grabs > 32-bit superreg. > > > Can one do the same for sources? > > Yes, this is just modifier for printing,

On Nov 24, 2009, at 12:19 PM, David Greene wrote: > On Tuesday 24 November 2009 14:12, Anton Korobeynikov wrote: >> Hello, David >> >>> How does ${dst:subreg32} work? >> >> This is just modifier provided to asmprinting code. Here, it seems, 16 >> bit register is passed to asmprinter, but it sees modifier and grabs >> 32-bit superreg. >>

On Wednesday 24 September 2008 02:10, Evan Cheng wrote: > > I wrote a pattern that looks something like the above in form, but how > > do I tell the selection DAG to prefer my pattern over another that > > already exists. I can't easily just disable that other pattern > > because > > it generates Machine Instruction opcode enums that are assumed to be > >

Chris Lattner wrote: > On Sep 23, 2008, at 11:26 AM, David Greene wrote: > >> Are there any examples of using tablegen to generate multiple machine >> instructions from a single pattern? Or do these cases always have >> to be >> manually expanded? > > PPC has a bunch of examples, for example: > > // Arbitrary immediate support. Implement in terms of

Jakob Stoklund Olesen <jolesen at apple.com> writes: >> What happens if the result of the above pattern using COPY_TO_REGCLASS >> is spilled? Will we get a 64-bit store or a 128-bit store? > > This behavior isn't affected by the change. FR64 registers are spilled > with 64-bit stores, and VR128 registers are spilled with 128-bit > stores. > > When the

On Wednesday 02 December 2009 17:24, Eli Friedman wrote: > On Wed, Dec 2, 2009 at 3:08 PM, David Greene <dag at cray.com> wrote: > > On Wednesday 02 December 2009 16:51, Eli Friedman wrote: > >> On Wed, Dec 2, 2009 at 2:44 PM, David Greene <dag at cray.com> wrote: > >> > I'm working on some of the AVX insert/extract instructions.  They're >

I have the following selection DAG: SelectionDAG has 9 nodes: t0: ch = EntryToken t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 t16: i32,ch = load<LD1[%ptr](tbaa=<0x10023c9f448>), anyext from i8> t0, t2, undef:i64 t15: v16i8 = BUILD_VECTOR t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16 t11: ch,glue = CopyToReg t0, Register:v16i8 %V2, t15

Hi all, The machine I am targeting has some special requirements for some operations, say: ADD or1, ir1, r5 would add ir1 (input reg 1) and r5 and put the result in or1 (output reg 1). The point id that input and output regs have to go paired (this meaning an addition of ir1 with whatever always goes to or1, or an in general irX + whatever goes to orX). AFAIK, InstrInfo.td only allow

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One way to do this is to handle this in the AsmPrinter, with operand modifiers. For example, on x86 there are instructions with ${dst:call} in their asm string. The "call" part is interpreted as an operand modifier. The assembly printer looks for the "call" modifier on MachineOperand::MO_Immediate operands (in X86ATTAsmPrinter::printOperand), which lets it perform custom

I've upgraded one of my client boxes to Windows 64 bit edition but now it cannot login to the Samba PDC, instead it gives a RPC error after entering the password. The Win32 boxes can still login fine. I can get accounts without admin rights to login but those with the rights are given a message stating "The system cannot log you on due to the following error: A remote procedure call