similar to: [LLVMdev] Custom delay slot insertion

Hi, Have you try to directly describe such patterns in tblgen file? Like this: (brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset) MIPS backend does that. I also do this in my own backend, and seem to be working fine. On Mon, Jan 7, 2013 at 11:55 AM, Vikram Singh <vsp1729 at gmail.com> wrote: > I have seen that most of the targets do comparison and branching > in two separate

I have seen that most of the targets do comparison and branching in two separate instructions e.g. 'cmpl' followed by 'br' in x86 or the like. LLVM IR is also in same manner. I want to implement comparison+branching in one instruction like beq r1, r2, .label #if r1==r2 then jump to .label How to merge two instruction into one. Regards Vikram Singh -- View this

There is format in sparc <pre> subcc %r1, %r2, %r3 bne .label </pre> I want instruction like this <pre> bne %r1, %r2, .label </pre> </BR> I am referring to sparc code for this implementation (llvm-3.1).</BR></BR> 1. Should I change the SPBranch and BCOND structs in .td file.</BR> 2. Should I change BuildMI constructs in

Hi In sparc ABI the arguments are saved by the callee in the caller stack frame. Q. What to do to save them in callee stack frame itself. for example by default this is generated sti r2, -2(fp) sti r3, -3(fp) Instead how to generate sti r2, 4(fp) sti r3, 5(fp) The Indices are just for explanation. The matter is In sparc they are -ive which means in the caller

I want to generate the instruction like addi 40, r3 ! i.e. r3 = r3 + 40 The format i wrote is def ADDI : F1<opcode, (outs IntRegs:$dst), (ins IntRegs:$dst, i32imm:$imm) "addi $imm, $dst", [(set $IntRegs:$dst, (add $IntRegs:$dst, i32imm:$c))] but it is not compiling. what should be the format. vikram -- View this message

On Sun, Aug 2, 2009 at 2:06 PM, Carter Cheng<carter_cheng at yahoo.com> wrote: > I was looking over the experimental MIPS backend and noticed that it has a delay slot pass which just inserts nops into the delay slots. I assume it should be possible to do a bit better than this. Is there an existing pass which "fills" delay slots or would I have to write one if I wanted slightly

The Sparc, Microblaze, and Mips code generators implement branch delay slots. They all seem to exhibit the same bug, which is not surprising since the code is very similar. If I compile code with this snippit: while (n--) *s++ = (char) c; I get this (for the Microblaze): swi r19, r1, 0 add r3, r0, r0 cmp r3, r3, r7 beqid r3,

You need to add your target to autoconf/configure.ac. Here are the directions from http://llvm.org/docs/WritingAnLLVMBackend.html To get LLVM to actually build and link your target, you need to add it to the TARGETS_TO_BUILD variable. To do this, you modify the configure script to know about your target when parsing the --enable-targets option. Search the configure script for TARGETS_TO_BUILD,

On Dec 14, 2010, at 3:46 PM, Richard Pennington wrote: > Notice that the label $BB0_1 is missing. If I disable filling in the > branch delay slots, I get: Is this with the latest SVN HEAD version of LLVM or some other version? The delay slot filler and many other things have been updated for the Microblaze backend. In particular, the commit r120095 for the MBlaze backend fixed some issues

Hi sam, On 12/06/2012 17:30, sam wrote: > Hi Ivan, > > The assertion was happening because I wasn't checking after the first > attempt failed. The first packet was failing and so it was ended, and > then the packetizer attempted to add it to the next packet without > checking for available resources. However this highlights probably the > real problem - my packetizer

Hi, I'm writing a pass which needs to insert an intrinsic in for my target, but I'm not sure how to create the call. I've tried defining a function, with the target intrinsic as its name, and then creating a new CallInst to call it. But how am I supposed to declare this function as an intrinsic? Thanks, Sam -- View this message in context:

Hi Ivan, The assertion was happening because I wasn't checking after the first attempt failed. The first packet was failing and so it was ended, and then the packetizer attempted to add it to the next packet without checking for available resources. However this highlights probably the real problem - my packetizer is unable to find resources for the first instruction, or any of my

Thanks for your help, Wei-Ren and Anton. However since I am doing some experiments with klee( http://klee.llvm.org/GetStarted.html) and llvm-gcc seems to have better compatibility with it. So I still hope that I can use llvm-gcc:-) Hongxu Chen On Sat, Mar 16, 2013 at 3:35 PM, 陳韋任 (Wei-Ren Chen) [via LLVM] < ml-node+s1065342n56013h94 at n5.nabble.com> wrote: > Hi Chen, > >

On 07/13/2012 04:30 PM, Duncan Sands wrote: > Hi, > >> I found the -postdomfrontier pass in *llvm*.org/docs/Passes.html, but >> 'opt' does not accept it. I could not find the relevant codes in >> PostDominance.cpp in SVN trunk, but I found some relevant codes here >> http://opensource.apple.com/source/clang/clang-137/src/lib/Analysis/PostDominators.cpp.

Hi shadowkernel, > I searched the archives and found > http://llvm.1065342.n5.nabble.com/post-dominance-frontier-fix-td10221.html > http://llvm.1065342.n5.nabble.com/Is-there-a-control-dependence-graph-builder-td35919.html#a35921 > http://llvm.1065342.n5.nabble.com/post-dominance-frontier-td6783.html > > It seems none of them are relevant. Could you give me more hints about

Thank your reply. Pankaj. Actually, I have done it very similar to yours. But I think for my demand, it is better to implement in Front End. Maybe I will re-implement it later in clang. ---------- Forwarded message ---------- From: Pankaj Gode [via LLVM] <ml-node+s1065342n59345h22 at n5.nabble.com> Date: Mon, Jul 15, 2013 at 2:35 PM Subject: Re: Regarding scope information for variable

On 12/14/2010 04:28 PM, Wesley Peck wrote: > On Dec 14, 2010, at 3:46 PM, Richard Pennington wrote: >> Notice that the label $BB0_1 is missing. If I disable filling in the >> branch delay slots, I get: > > Is this with the latest SVN HEAD version of LLVM or some other version? The delay slot filler and many other things have been updated for the Microblaze backend. In

-----Original Message----- From: Vikram S. Adve [mailto:vadve at cs.uiuc.edu] Sent: Sunday, January 25, 2004 7:16 AM To: Joseph E. Grzywacz Subject: RE: [LLVMdev] Basic Blocks: Bytecode -> Native Code [Joseph, I'm sending this again because I didn't copy the list the first time.] Yes, this is true for the Sparc back-end. In fact, it is a fundamental assumption that is relied on by

Hi, I was looking over the experimental MIPS backend and noticed that it has a delay slot pass which just inserts nops into the delay slots. I assume it should be possible to do a bit better than this. Is there an existing pass which "fills" delay slots or would I have to write one if I wanted slightly more optimal code? (anyone have any references?) Thanks in advance.

On 12/14/2010 04:32 PM, Richard Pennington wrote: > On 12/14/2010 04:28 PM, Wesley Peck wrote: >> On Dec 14, 2010, at 3:46 PM, Richard Pennington wrote: >>> Notice that the label $BB0_1 is missing. If I disable filling in the >>> branch delay slots, I get: >> >> Is this with the latest SVN HEAD version of LLVM or some other version? The delay slot filler and