similar to: [LLVMdev] trying to generate a simple inline asm

I am compiling the following code for the MIPS architecture: unsigned char trunc(float f) { return (unsigned char) f; } and it produces the following assembly (directives removed for convenience: trunc: trunc.w.s $f0, $f12 mfc1 $2, $f0 jr $ra nop However, this does not seem to produce the correct output for negative numbers. When I run the following code, I get

> > I didn't realize the code was undefined, I'll let my professor know; but > for code comparison purposes we're still seeking advice on producing the > output that matches the other compilers (even if it involves doing a > translation on the .ll file or additional translation to the produced > assembly). We can't fairly compare the code if it doesn't do the

I'm happy to send you my patch as it stands today. It's not cleaned up yet all or tested thoroughtly but you can look at what I'm doing and maybe suggest some alternate paths and if it's not a matter of redoing everything, I would consider making some changes. Here is a sample stub: Consider this line of code: extern float fpff(float); We have no idea if this is a mips16 or

On 01/28/2014 06:29 PM, Eric Christopher wrote: > Uhhhh... > > -eric > > On Tue, Jan 28, 2014 at 4:56 PM, reed kotler <rkotler at mips.com> wrote: >> I would like to make the following member of AsmPrinter be protected >> >> >> void EmitInlineAsm(StringRef Str, const MDNode *LocMDNode = 0, >> InlineAsm::AsmDialect

> So in summary, each step is ABI compatible with the previous step. The linker will ensure that the end-user doesn't try to do the second step before the first step is finished since it will refuse to link a binary that contains both O32 and O32+fp64. It will produce an O32 binary given a combination of O32+fpxx, and similarly a O32+fp64 binary given a combination O32+fpxx and O32+fp64.

On Mon, Jun 23, 2014 at 2:45 AM, Daniel Sanders <Daniel.Sanders at imgtec.com> wrote: >> There are a lot of MIPS ABIs. > > Yes, and we've discovered that there seem to be incompatible extensions to some of these ABI's too. :) > >> I'm pretty sure Imagination Technologies working up a new abi right now. > > Not exactly. We're not working on any

Hi, I installed XEN 3.4-testing version without much problems in CentOS 5.3 running on quadcore Intel Nahelam processors using the following installation steps (as in the README) : <steps> hg clone http://xenbits.xensource.com/xen-3.4-testing.hg` cd xen-unstable.hg make world make install make linux-2.6-xen-config CONFIGMODE=menuconfig make linux-2.6-xen-build make linux-2.6-xen-install

This came about in trying to implement some stubs used by gcc mips16 for allowing floating point interoperability with mips32. You get the following looking code from gcc -mips16: # Stub function for foovf (float) .section .mips16.fn.foovf,"ax", at progbits .align 2 .set nomips16 .set nomicromips .ent __fn_stub_foovf .type __fn_stub_foovf, @function __fn_stub_foovf: la

> It is exactly intended to handle section names as what they are -- > section names. The only reason it works with GCC is because it writes an > assembler stream. +1 Reed, this fails in gcc if you do LTO, no? > Joerg Cheers, Rafael

On Wed, Jun 18, 2014 at 2:03 AM, Matheus Almeida <Matheus.Almeida at imgtec.com> wrote: >> Why Imagination Technologies do not offer the latest MIPS ABI document download link just like the ISA docs? > It's something we're considering to do and the documents should be available at some point in the [hopefully] not too distant future. > >> then why GCC disagree with

call void @llvm.branchlike(label %thelabel) Is it possible to give a label/BasicBlock* to an intrinsic? Similar to labels for branches. No label type is currently defined in Intrinsics.td, but would it be possible to add it there and ValueTypes.td? But I also want to take the address and put it into a physical register and emit a desired x86 instruction. Assuming I have the label, I should be

> We also wanted the stubs to be real functions to llvm. That allows them to > participate properly > in optimization of various levels (including LTO). They can even be inlined. > There are other > planned optimizations that would not work if they were not legitimate > functions. I am not saying that the functions should not exist in the IL, just that they should not be inline

On 04/24/2013 03:47 PM, Rafael Espíndola wrote: > On 24 April 2013 18:30, reed kotler <rkotler at mips.com> wrote: >> There are a lot of issues. >> >> For one, the function I'm compiling is a mips16 function but the stubs being >> created are mips32 functions. >> > This looks similar to thumb x 32 bit arm. Wouldn't a similar solution > work for

Hello. I come back to this thread. But I want to ask a slightly different question. Is there a way to have LLVM IR language intrinsics that are given at construction time a string that is written at assembly generation time as it is? (so, basically having placeholders of strings in LLVM that remain untouched until the end, including code generation time.) More exactly, I would