similar to: [LLVMdev] Flag and Glue

Displaying 20 results from an estimated 800 matches similar to: "[LLVMdev] Flag and Glue"

2013 Apr 15
0
[LLVMdev] Flag and Glue
A similar casualty is that we have a bunch of nonsensically named variables `const DataLayout *TD` as residue from the TargetData -> DataLayout transition :| -- Sean Silva -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130415/17355dab/attachment.html>
2013 Apr 16
1
[LLVMdev] Flag and Glue
On Mon, Apr 15, 2013 at 4:50 PM, Sean Silva <silvas at purdue.edu> wrote: > A similar casualty is that we have a bunch of nonsensically named > variables `const DataLayout *TD` as residue from the TargetData -> > DataLayout transition :| > Good catch! I kicked off with 179601 fixing it in the DataLayout class itself. Eli -------------- next part -------------- An HTML
2013 Apr 15
1
[LLVMdev] Flag and Glue
On Apr 15, 2013, at 4:50 PM, Sean Silva <silvas at purdue.edu> wrote: > A similar casualty is that we have a bunch of nonsensically named variables `const DataLayout *TD` as residue from the TargetData -> DataLayout transition :| Patches that fix these sorts of issues are pre-approved. Go for it :-) -Chris
2019 Dec 10
3
Glue two instructions together
Hi, for DAG-to-DAG instruction selection I’ve implemented a pattern, which creates from one SDNode two instructions, something like: def: Pat<(NEW_SDNODE REG:$r1), (INST_OUT (INST_IN), REG:$r1)>; where INST_IN doesn't accepts any inputs and INST_OUT accepts two inputs - one returned by INST_IN and REG;$r1. Is there any possibility to ‘Glue’ two instruction created
2017 Sep 15
0
Changes to 'ADJCALLSTACK*' and 'callseq_*' between LLVM v4.0 and v5.0
Hi Martin, Pseudo CALLSEQ_START was changed in r302527, commit message contains details on the changes. However CALLSEQ_END was not modified. If your made changes to ADJCALLSTACKUP to add additional argument, that may result in error. Thanks, --Serge 2017-09-15 19:09 GMT+07:00 Martin J. O'Riordan via llvm-dev < llvm-dev at lists.llvm.org>: > Hi LLVM-Devs, > > I have managed
2017 Sep 19
1
Changes to 'ADJCALLSTACK*' and 'callseq_*' between LLVM v4.0 and v5.0
Hi Serge, Thanks for your help. I have looked at the change log, and so far as I can tell, my implementation is pretty much identical to all of the in-tree targets, but I’m missing something and can’t see what it is. I have simplified my TD description to just: def MyCallseqStart : SDNode<"ISD::CALLSEQ_START", SDCallSeqStart<[SDTCisVT<0, i32>,
2017 Sep 15
2
Changes to 'ADJCALLSTACK*' and 'callseq_*' between LLVM v4.0 and v5.0
Hi LLVM-Devs, I have managed to complete updating our sources from LLVM v4.0 to v5.0, but I am getting selection errors for 'callseq_end'. I am aware that the 'ADJCALLSTACKUP' and 'ADJCALLSTACKDOWN' patterns have changed, and have added an additional argument to the TD descriptions for these. There are interactions with 'ISD::CALL' and 'ISD::RET_FLAG',
2019 Dec 11
2
Glue two instructions together
You could hardcode a register for the pseudo instruction to use in the td file. The register allocator will make sure not to clobber it. let uses = [ R1 ], defs = [ R1 ] in { def MYINST : Pseudo<> } On Wed, Dec 11, 2019 at 10:25 AM Przemyslaw Ossowski via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I have one more question regarding expanding pseudo instruction. > >
2013 Feb 02
0
[LLVMdev] Moving return value registers from MRI to return instructions
MachineRegisterInfo is maintaining a list of live-out registers for the MachineFunction. It contains the return value registers, and is typically created by XXXISelLowering::LowerReturn(). Various passes after instruction selection need to look at this list to determine which physical registers are live in return blocks. Eventually, the register allocators copy these live-out registers onto the
2016 Apr 27
2
[Sparc] builtin setjmp / longjmp - need help to get past last problem
Hi, I'm implementing __builtin_setjmp and __builtin_longjmp for Sparc 32 bit processors (64 bit later, time allowing). I'm basing the code on the PowerPC version, which itself is based on the X86 version. This code is very nearly working, and I've had it working for -O0 optimisation (with a slightly different version to that below), so I know it's close. However, the PowerPC
2019 Jul 11
6
Glue to connect two nodes in LLVM backend
Hello everyone, I wanted to attach a node without affecting the present nodes in any way. I tried to use MVT::Glue for that but I think I'm missing something as I could not achieve the below state. LUI LUI | | ADDI ----GLUE---- ADDI | store I've few question about this and Glue node in general, I'll be happy to get some help on
2020 Jul 15
2
read.csv fails in R console in Ubuntu terminal but works in RStudio after R 3.6.3 upgrade to R 4.0.2
Hi, I am trying to download some data using read.csv and it works perfectly in RStudio and fails in the R console in the terminal in Ubuntu 18.04 after upgrading from R 3.6.3 to 4.0.2. Before upgrading this worked in the R console in the terminal also without any issues. Why would that be? How to fix this? Below please find R code output and sessionInfo(). *Works in RStudio* >
2017 Jun 24
9
IMPORTANT: LLVM.org server move complete (SVN impact please read)
LLVMers, We have completed the move to the new server for LLVM.org. One casualty of this move was that svn.llvm.org was NOT enabled at this time. There is a new certificate for LLVM.org and HTTPS is enabled for the website. We know of a few issues with some of the webpages but will be working them out over the next few days. Please do not hesitate to contact llvm-admin at lists.llvm.org with
2010 Jan 19
1
[LLVMdev] ComplexPattern
Hi, I was wondering if someone could explain precisely what the ComplexPattern tablegen class does? Here's the first line of the definition (from TargetSelectionDAG.td) for reference: class ComplexPattern<ValueType ty, int numops, string fn, list<SDNode> roots = [], list<SDNodeProperty> props = [],
2017 Jun 28
2
Videos from past Dev meetings gone?
Are the videos another casualty of the server move? Following the links down to a video to here: http://llvm.org/devmtg/2014-10/Videos/Adding%20and%20Optimizing%20a%20Subtarget%20for%20MIScheduler-720.mov Sends me to a dead link. Do we know when this is expected to work again? -------------- next part -------------- An HTML attachment was scrubbed... URL:
2016 Feb 02
2
New register class and patterns
> On Feb 1, 2016, at 16:53, Rail Shafigulin <rail at esenciatech.com> wrote: > > > > On Fri, Jan 29, 2016 at 10:03 PM, Matt Arsenault <arsenm2 at gmail.com <mailto:arsenm2 at gmail.com>> wrote: > > > On Jan 29, 2016, at 13:25, Rail Shafigulin via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > > >
2017 Jun 27
3
IMPORTANT: LLVM.org server move complete (SVN impact please read)
Hi, After the move I have problems with svn checkout of trunk and 4.0 branch. I get the whole bunch of different errors during checkout, including: svn: E000054: Error running context: Connection reset by peer svn: E000060: Operation timed out svn: E000104: Error retrieving REPORT: Connection reset by peer svn: E120106: ra_serf: The server sent a truncated HTTP response body. Sometimes I'm
2011 Apr 08
2
Quantile Regression and R
Sir or Madam: I am new to R and the use of quantile regeression. In addition, I am a finance person not a true statistcian. Basic regression form is Y = (Coefficient * Variable) + Error Term I have results from a quantile regression where I used the Barro and Roberts method with bootstrapping for standard errors. I am now taking another set of data and applying the quantile regression
2011 Oct 09
0
[LLVMdev] How to stick two instructions together?
Hi all, Currently, I run into a problem in selecting a multiply-add-forward instruction in my backend. ... %bin = xor i16 %1, %2 (any binary operation) %mul = mul i16 %3, %4 %add = add i16 %mul, %bin should generate a multiply-add-forward instruction as XOR R0, R1, R2 ; R1 xor R2 -> R0 MULADDFWD R5, R3, R4 ; R3 * R4 + *result of (R1 xor R2)* -> R5 (Note the implicit operand of
2017 Nov 28
2
Debian Buster, bind_dlz, and apparmor
On 11/28/2017 2:38 AM, Rowland Penny via samba wrote: > On Mon, 27 Nov 2017 14:53:32 -0600 > Dale Schroeder via samba <samba at lists.samba.org> wrote: > >> Last week, Debian testing (Buster) added apparmor to the list of >> dependencies for its latest kernel release, apparently because >> systemd needs it.  Recently, I noticed my first casualty - bind9 - >>