similar to: [LLVMdev] Target Instructions

On May 30, 2013, at 11:35 AM, Jafar J <pluck90 at hotmail.com> wrote: > Hi Jim, > > The idea of reducing the switching activity between the instructions works by reducing the hamming distance between tow consecutive binary strings across the basic block, or reducing the number of the different bits between two consecutive instructions. This is why I need the exact complete

Hi Jim, The idea of reducing the switching activity between the instructions works by reducing the hamming distance between tow consecutive binary strings across the basic block, or reducing the number of the different bits between two consecutive instructions. This is why I need the exact complete encoding in plain 0’s and 1’s, to be as precise as possible during the scheduling process. I did

Hi Jafar, That’s not quite what I meant. Why do you need to know the exact encoding at all? The instruction opcode+operands should have all the semantic information you need without ever looking at the actual encoding. -Jim On May 30, 2013, at 11:08 AM, Jafar J <pluck90 at hotmail.com> wrote: > Yes your absolutely right, the Opcode and the Operands in each machine instruction are

Yes your absolutely right, the Opcode and the Operands in each machine instruction are sufficient to generate the final binary representation of the MachineInstruction but not exactly. If you take a look at the format of each MIPS instruction, you’ll see that there are some fixed bits for each instruction which are not available inside the machine instruction object –From what I saw so far-.

Thanks, that helps. The code emitter is definitely not the way you want to go about solving this problem, though. Are the instruction opcode (MachineInstr::getOpcode()) and the operand values not sufficient? All the information present in the encoding should be inferable from those, as that’s where the encoding comes from. -Jim On May 30, 2013, at 10:12 AM, Jafar J <pluck90 at

I need to represent each instruction with its (32-bit) binary encoding, and I reached to a conclusion that I could get the encoding through the MipsCodeEmitter. What I’m trying to do exactly is write a scheduler which tries to minimize the switching activity between the scheduled instructions in each basic block. One way to do that is by representing each instruction with its complete binary

What are you actually trying to do? The code emitters have nothing to do with the post-RA scheduler. -Jim On May 30, 2013, at 6:23 AM, Jafar J <pluck90 at hotmail.com> wrote: > Hello, > > Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter.h to PostRASchedulerList.cpp, but when I rebuild

Hello, Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter.h to PostRASchedulerList.cpp, but when I rebuild the compiler I get an error that says “/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h fatal error: MipsGenRegisterInfo.inc file not found”. I’m assuming that the MipsGenRegisterInfo.inc is not yet

Hi Andy, The thing is that I was trying to build a sched graph in other places than these two standard scheduling passes. For instance, in pre-emit. I would like to reschedule a basic block on my vliw target just before assembly emission. I tried to add SUnits for hazards in an experiment, but this gave very weird errors... even while allocating extra space in SUnits vector. For some function, I

On Feb 21, 2013, at 9:11 AM, Jonas Paulsson <jonas.paulsson at ericsson.com> wrote: > Hi, > > I am trying to add Hazard scheduling nodes after buildSchedGraph(), with a scheduler derived from ScheduleDAGInstrs. I get weird errors, so I wonder what I am doing wrong? > > What I am doing right now is: > > I have a created MI with opcode HAZARD that does not have

Hi, I am trying to add Hazard scheduling nodes after buildSchedGraph(), with a scheduler derived from ScheduleDAGInstrs. I get weird errors, so I wonder what I am doing wrong? What I am doing right now is: I have a created MI with opcode HAZARD that does not have parent, and I greate a SUnit(HazardMI). I use this one HazardMI for all hazard nodes. I remove all edges using removePred. I insert

Hi all, When compiling some programs using the Mips backend i'm getting this assert message on lib/CodeGen/LiveInterval.cpp:227: "Range is not entirely in interval!" I don't know yet if it's something that is missing on the backend code or why the range to be removed it outside the interval, does anyone have any clue? A more detailed output is attached. The program i tried

Does it make a difference if you give the "-target" option to clang? $ clang -target mips-linux-gnu ch8_3.cpp -o ch8_3.bc -emit-llvm -c The .s file generated this way looks quite different from the one in your email. On Tue, Feb 19, 2013 at 5:06 PM, Jonathan <gamma_chen at yahoo.com.tw> wrote: > I didn't have Mips board. I compile as the commands and check the asm >

Hi, I am hoping that someone can help me figure out how to prevent the insertion of "memcpy" from the assembly source. My target is an instruction set simulator that doesn't support this. Thank you for your valuable time. Wolf *Here are my compile commands:* $ clang -emit-llvm -fno-builtin -o3 --target=mips -S matrix_float.c -o vl_matrix_float.ll $ llc vl_matrix_float.ll *IR

I didn't have Mips board. I compile as the commands and check the asm output as below. 1. Question: The distance of caller arg[4] and arg[5] is 4 bytes. But the the callee get every arg[] by 8 bytes offset (arg_ptr1+8 or arg_ptr2+8). I assume the #BB#4 and #BB#5 are the arg_ptr which is the pointer to access the stack arguments. 2. Question: Stack memory 28($sp) has no initial value. If

Hi Pekka, > Has anyone studied how much work it would be to implement an integrated > allocator/scheduler in LLVM now? Not to my knowledge. > Another solution (which we use in TCE) is to use register renaming. You do it in LLVM? Do you plan to upstream it? Also, I do not know your target/goal, but do you look at global scheduling at all? Thanks. Sergei -- Qualcomm Innovation

I'm just passing this patch on to the list as I know Brian is busy and I had proded him to file the bug report. http://llvm.org/bugs/show_bug.cgi?id=14721 "binutils on OpenBSD is quite old, which causes the build on mips64el to fail on MipsJITInfo.cpp - it complains of illegal operands. The attachment patches it so that it will build. All the patch does is replace the register aliases

i have this code typedef long long L; typedef integer I; void test2(auto L p0, auto L p1, auto L p2, auto L p4, ...) { va_list select; va_start (select, p4); report( va_arg(select,L) ); report( va_arg(select,I) ); report( va_arg(select,L) );

Could you file a bug? On Wed, Feb 27, 2013 at 2:47 AM, Stavropoulos Nikos < n.stavropoulos at think-silicon.com> wrote: > i have this code > > typedef long long L; > typedef integer I; > void test2(auto L p0, auto L p1, auto L p2, auto L p4, ...) > { > va_list select; > > va_start (select, p4); > > report( va_arg(select,L) ); > report(

It's not building: usr/include/c++/4.0.0/bits/stl_queue.h: In member function 'void std::priority_queue<_Tp, _Sequence, _Compare>::push(const typename _Sequence::value_type&) [with _Tp = llvm::SUnit*, _Sequence = ll\ vm::container_reference_wrapper<std::vector<llvm::SUnit*, std::allocator<llvm::SUnit*> > >, _Compare = <unnamed>::td_ls_rr_sort]':