Displaying 20 results from an estimated 1000 matches similar to: "[LLVMdev] Hit a snag while attempting to write a backend - any advice?"
2014 Dec 10
2
[LLVMdev] Virtual register problem in X86 backend
Hi,
Thx for your help...
Here is the IR code:
; ModuleID = 'foo_bar.c'
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
@.str = private unnamed_addr constant [6 x i8] c"MAIN\0A\00", align 1
; Function Attrs: nounwind uwtable
define i32 @main(i32 %argc, i8** %argv) #0 {
entry:
%retval = alloca i32,
2014 Oct 28
2
[LLVMdev] Problem in X86 backend (again)
Hi,
I'm still having problems implementing my custom inserter in the X86 backend.
I found a solution to my last problem (http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-October/078296.html), by using a virtual register.
The binary works when it's compiled in -O0, but not in -O1,-O2,...
I really can't figure what I'm doing wrong... Any idea?
Here is the code of my custom
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
Hi,
below is an output of "llc -march=r600 -mcpu=cayman -print-before-all -debug-only=regalloc file.shader" command from llvm3.2svn.
The register coalescing pass crashes when joining vreg12:sel_z with vreg13 registers, because it tries to access the interval liveness of vreg13... which is undefined.
I don't know if it's a bug of the pass, or if my backend should do something
2011 Mar 28
0
[LLVMdev] Possible missed optimization?
On Mar 26, 2011, at 4:09 PM, Borja Ferrer wrote:
> You can look at the output of -debug-only=regcoalescing to see what is going on.
>
> This is the debug output i've got, some information is a bit cryptic for me so next is what i understood:
>
> ********** SIMPLE REGISTER COALESCING **********
> ********** Function: foo
> ********** JOINING INTERVALS ***********
>
2013 Feb 08
0
[LLVMdev] help with X86 DAG->DAG Instruction Selection
Hi Peng,
Can you please open a bugzilla and attache the LL file ? Can you please reproduce it on ToT ?
Thanks,
Nadav
On Feb 7, 2013, at 9:08 PM, Peng Cheng <gm4cheng at gmail.com> wrote:
> I have an llvm ir, which generates the following machine code using llc (llvm 3.0 on win32) after # *** IR Dump After X86 DAG->DAG Instruction Selection ***:
>
> The first three lines
2011 Mar 26
2
[LLVMdev] Possible missed optimization?
>
> You can look at the output of -debug-only=regcoalescing to see what is
> going on.
>
> This is the debug output i've got, some information is a bit cryptic for me
so next is what i understood:
********** SIMPLE REGISTER COALESCING **********
********** Function: foo
********** JOINING INTERVALS ***********
entry:
16L %vreg0<def> = COPY %R25R24<kill>;
2013 Feb 08
2
[LLVMdev] help with X86 DAG->DAG Instruction Selection
I have an llvm ir, which generates the following machine code using llc
(llvm 3.0 on win32) after # *** IR Dump After X86 DAG->DAG Instruction
Selection ***:
The first three lines and the last two lines alone together are used to
compute "sin" for some double number.
- line 1: move the stack pointer down 8
- line 2: copy the updated stack pointer to a base register
- line 3: copy a
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
Ok, after a long detour I am back to where I have started. I think there is
a problem at dep DAG construction. Let me try to convince you.
Here is the C code we are dealing with:
push ()
{
struct xx_stack *stack, *top;
for (stack = xx_stack; stack; stack = stack->next)
top = stack;
yy_instr = top->first;
}
If the loop never iterates, "top" will have
2012 Jun 14
1
[LLVMdev] Assert in live update from MI scheduler.
Sergei,
Absolutely right, the copy/ldriw should not be reordered. I was attempting to explain that I consider it a phi-elimination bug, not a DAG builder bug. Liveness will also have problems with this code in the long run.
To avoid confusion, I filed PR13112: Phi elimination generates uninitialized vreg uses, and disabled the SSA check until its fixes in r158461.
However, your C code is also
2018 Apr 23
2
pre-RA scheduling/live register analysis optimization (handle move) forcing spill of registers
Hi,
I have a question related to pre-RA scheduling and spill of registers.
I'm writing a backend for two operands instructions set, so FPU operations result have implicit destination.
For example, the result of FMUL_A_oo is implicitly the register FA_ROUTMUL.
I have defined FPUaROUTMULRegisterClass containing only FA_ROUTMUL.
During the instruction lowering, in order to avoid frequent spill
2014 Oct 29
2
[LLVMdev] Problem in X86 backend
Hi Julien,
> On Oct 28, 2014, at 2:14 AM, Rinaldini Julien <julien.rinaldini at heig-vd.ch> wrote:
>
> Hum, in fact, I'm still a bit lost ;)
>
> It seems to works in -O0, but in -O1, -O2 and -O3, I got this error (+ the dump of the function):
>
> # Machine code for function foo: Post SSA
> Function Live Ins: %RDI in %vreg7
>
> BB#0: derived from LLVM BB
2013 May 13
1
[LLVMdev] Tracking down a SELECT expansion to predicated moves
I've inherited some target code, but there is no SELECT lowering in my
target. But somewhere/somehow SELECT is being transformed into a
predicated move. I've traced SELECT everywhere in Codegen/SelectionDAG.
Any ideas on tracking this down to the point in Codegen
lowering/dag-conversion to a predicated series? Again, I do not have a
lowering rule in my target for SELECT.
If I do a IR
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
Andy,
You are probably right here - look at this - before phi elimination this
code looks much more sane:
# *** IR Dump After Live Variable Analysis ***:
# Machine code for function push: SSA
Function Live Outs: %R0
BB#0: derived from LLVM BB %entry
%vreg5<def> = IMPLICIT_DEF; IntRegs:%vreg5
%vreg4<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg4
2014 Oct 24
2
[LLVMdev] Virtual register def doesn't dominate all uses
Hi!
During my backend development I get the error message for some tests:
*** Bad machine code: Virtual register def doesn't dominate all uses. ***
(C source-code, byte-code disassembly and printed machine code at the end of the email)
The first USE of vreg4 in BB#1 has no previous DEF in BB#0 or #1. But why? I can't see how the LLVM byte-code is transformed to the lower machine code.
2018 Apr 12
2
How to specify the RegisterClass of an IMPLICIT_DEF?
Hi,
I'm implementing the built_vector as an IMPLICIT_DEF followed by INSERT_SUBREGs. This approach is the one of the SPARC architecture.
def : Pat<(build_vector (f32 fpimm:$a1), (f32 fpimm:$a2)),
(INSERT_SUBREG(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
(i32 (COPY_TO_REGCLASS (MOVSUTO_A_iSLo (bitcast_fpimm_to_i32 f32:$a1)), FPUaOffsetClass)), A_UNIT_PART),
2012 Jun 13
2
[LLVMdev] Assert in live update from MI scheduler.
On Jun 13, 2012, at 1:15 PM, Sergei Larin <slarin at codeaurora.org> wrote:
> Andy,
>
> You are probably right here – look at this – before phi elimination this code looks much more sane:
>
> # *** IR Dump After Live Variable Analysis ***:
> # Machine code for function push: SSA
> Function Live Outs: %R0
>
> BB#0: derived from LLVM BB %entry
>
2017 Oct 13
3
Machine Scheduler on Power PC: Latency Limit and Register Pressure
> On Oct 13, 2017, at 1:46 PM, Matthias Braun <matze at braunis.de> wrote:
>
> Yes, I've run into the problem myself that the Pending queue isn't even checked with the tryCandidate() logic and so takes priority over all other scheduling decisions.
>
> I personally would be open to changes in this area. To start the brainstorming I could imagine that we move nodes
2017 Oct 13
2
Machine Scheduler on Power PC: Latency Limit and Register Pressure
Hi,
I've been looking at the Machine Scheduler on Power PC. I am looking only
at the pre-RA machine scheduler and I am running it in the default
bi-directional mode (so, both top down and bottom up queues are
considered). I've come across an example where the scheduler picks a poor
ordering for the instructions which results in very high register pressure
which results in spills.
2014 Oct 29
2
[LLVMdev] Virtual register def doesn't dominate all uses
Hi Quentin,
yes, this happens quite late. With the Option --debug-pass=Structure it's in or after "Assembly Printer".
I do have a very simple DAGToDAGISel::Select() method:
SDNode *MyTargetDAGToDAGISel::Select(SDNode *N)
{
SDLoc dl(N);
// default implementation
if (N -> isMachineOpcode()) {
N -> setNodeId(-1);
return NULL; // Already selected.
}
SDNode
2014 Nov 01
2
[LLVMdev] Virtual register def doesn't dominate all uses
Hi Quentin,
Am 01.11.2014 um 00:39 schrieb Quentin Colombet <qcolombet at apple.com>:
>
> On Oct 31, 2014, at 11:00 AM, Boris Boesler <baembel at gmx.de> wrote:
>
>> Hi Quentin,
>>
>> I added some debug output (N->dump()) in ::Select(SDNode*N) and compared it to the dot/Graphviz output (-view-legalize-types-dags; the last one with correct code). I