similar to: [LLVMdev] Obtaining and using block frequencies in MachineScheduler.cpp

Andy, Jacob, I have ported Hexagon MI scheduler to use the new scheduler infrastructure, but one of my tests triggers an assert in LiveInterval update. On the surface it does not make much sense to me, so I wonder if this is something you readily recognize, before I try to prop it open... The assert is: lib/CodeGen/LiveInterval.cpp:266: llvm::LiveRange*

...this is moving from llvm-commits to llvm-dev. On Feb 10, 2012, at 12:14 PM, Sergei Larin <slarin at codeaurora.org> wrote: > 1) Can a BB presented to the MI scheduler be _not_ terminated (end on a non > terminator MI) under any circumstances? Below you are speaking about "Empty > blocks, or blocks with only a single instruction that not a terminator..." - > What

I was handed a makefile which is used to compile a library and was told to figure out why the compilation is failing. There is a lot of output and at this point I'm not sure what is important and what is not. I'm trying to solve this problem in small steps, so if asked I can certainly provide more information. The first error that I see during compilation is

Andy, I've described that issue (see below) when you were out of town... I think I am getting more context on it. Please take a look... So, in short, when the new MI scheduler performs move of an instruction, it does something like this: // Move the instruction to its new location in the instruction stream. MachineInstr *MI = SU->getInstr(); if (IsTopNode) {

Thanks for the suggestion. I tried your fix. It worked for my particular case, but then I got a following error: clang-3.5: /home/rail/projects/escala_llvm/trunk/llvm-or1k/lib/CodeGen/RegisterPressure.cpp:39: void decreaseSetPressure(std::vector<unsigned int>&, llvm::PSetIterator): Assertion `CurrSetPressure[*PSetI] >= Weight && "register pressure underflow"'

Apologies if my questions sound dumb. They are provided below. On Wed, Apr 27, 2016 at 2:43 PM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > Are there any instructions (other than COPY) that use hardware > (allocatable) registers? > How do I find that out? > Could you show the instructions in the scheduling range? > How can I see instructions in the current

On 4/28/2016 2:11 PM, Rail Shafigulin wrote: > > On Thu, Apr 28, 2016 at 6:13 AM, Krzysztof Parzyszek > <kparzysz at codeaurora.org <mailto:kparzysz at codeaurora.org>> wrote: > > > IIRC, > > What is IIRC? If I remember correctly... -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Hi, I'm trying to understand why MachineScheduler does a poor job in straight line code in cases like the one in the attached debug dump. This is on AMDGPU, an in-order target, and the problem is that the IMAGE_SAMPLE instructions have very high (80 cycle) latency, but in the resulting schedule they are often placed right next to their uses like this: 1784B %140:vgpr_32 =

Hi Andy, Thanks for the explanations. Yes AMDGPU is in-order and has MicroOpBufferSize = 1. Re "issue limited" and instruction groups: could it make sense to disable the generic scheduler's detection of issue limitation on in-order CPUs, or on CPUs that don't define instruction groups, or some similar condition? Something like: --- a/lib/CodeGen/MachineScheduler.cpp +++

There are uses of R0 all over the place, even though R0 is not marked as live-in to any of the blocks that use it. For example: BB#45: derived from LLVM BB %sw.bb54 Predecessors according to CFG: BB#43 BB#44 DBG_VALUE %vreg287, %noreg, !"base" %vreg203<def> = LWZ <fi#5>, 0; mem:LD4[%args] GPR:%vreg203 %vreg204<def> = ADDI %vreg203, 3;

On Jul 22, 2013, at 11:50 AM, Tom Stellard <tom at stellard.net> wrote: > Hi, > > I'm working on defining a SchedMachineModel for the Southern Islands > family of GPUs, and I have two questions related to the > MachineScheduler. > > 1. I have a resource that can process 15 instructions at the same time. > In the TableGen definitions, should I do: > > def

Hi, I'm working on defining a SchedMachineModel for the Southern Islands family of GPUs, and I have two questions related to the MachineScheduler. 1. I have a resource that can process 15 instructions at the same time. In the TableGen definitions, should I do: def HWVMEM : ProcResource<15>; or let BufferSize = 15 in { def HWVMEM : ProcResource<1>; } 2. Southern Islands has

> On May 9, 2018, at 9:43 AM, Jonas Paulsson <paulsson at linux.vnet.ibm.com> wrote: > > Hi, > > I would like to ask what IssueWidth and NumMicroOps refer to in MachineScheduler, just to be 100% sure what the intent is. > Are we modeling the decoder phase or the execution stage? > > Background: > > First of all, there seems to be different meanings of

Hi, I would like to ask what IssueWidth and NumMicroOps refer to in MachineScheduler, just to be 100% sure what the intent is. Are we modeling the decoder phase or the execution stage? Background: First of all, there seems to be different meanings of "issue" depending on which platform you're on:

I have a small matrix where the columns represents a ranking and the values are the number of times each ranking was obtained eg 1 2 3 x 1 2 0 y 0 1 2 z 2 0 1 I'd like to be able to return an average of the ranking obtained average x 1.67 y 2.67 z 1.67 Whats the nicest way to do this? I'm new to the language and looking for an elegant solution :) Thanks Ben

If you want to create a version for the mips1 subtarget, going back in time will probably be a lot of work for you. If you want to modify the current version you might try the following: 1) Create a Mips1 predicate and use that to disable instruction patterns that match using non Mips1 instructions. 2) Use soft-float 3) You would need to reenable some commented out code used to implement

Hi Everybody, I'm working a project which requires assembly code for mips1 architecture for simulation purpose. I checked the latest LLVM3.2 version and found that the backend has been removed. I tried to replace the MIPS backed in LLVM3.2 by the old one in LLVM2.9 (which contains mips1) and adjust some routines to get the backend compiled. However, when llc is used to generate the assembly,

Hi Andy, >> Right now it seems that BeginGroup/EndGroup is only used by SystemZ, >> or? I see they are used in checkHazard(), which I actually don't see >> as helpful during pre-RA scheduling for SystemZ. Could this be made >> optional, or perhaps only done post-RA if target does post-RA >> scheduling? SystemZ does post-RA scheduling to manage decoder

Good Day list, Anyone know if there is a way to have the AgentCallBackLogin function play a voice file after the agent picks up the phone? If this is not an available feature, any ideas on the difficulty in making this feature? Example: Extensions.conf exten?=>?700,1,AgentCallbackLogin(${CALLERIDNUM}|?AnnounceCAllQue-TechSu pport?); ....... exten => s,6,Queue(queue1)

Hi to everyone, while working with the machine scheduler for a personal project, I came up with the necessity of inserting a backup boundary in the MachineSchedulerStrategy -- specifically, the PostGenericScheduler -- to hold a copy the scheduler's state, in order to implement a really trivial (and really inefficient) backtracking mechanism. This approach leads to a subtle "segmentation