similar to: [LLVMdev] Asm syntax of Mips m[tf]cX coprocessor instructions

Hi all, I'm experimenting with compiling some Mips code which is normally built with a gcc cross toolchain with clang instead. This code targets the Cavium Octeon, and uses some of that CPU's crypto engine features which are implemented in coprocessor 2. The inline asm for the crypto code uses instructions of the form "dmtc2 %0, 0xNNNN" - that is the coprocessor register is

Normal boot path on system with iommu support: swiotlb buffer will be allocated early at first and then try to initialize iommu, if iommu for intel or AMD could setup properly, swiotlb buffer will be freed. The early allocating is with bootmem, and could panic when we try to use kdump with buffer above 4G only, or with memmap to limit mem under 4G. for example: memmap=4095M$1M to remove memory

Normal boot path on system with iommu support: swiotlb buffer will be allocated early at first and then try to initialize iommu, if iommu for intel or AMD could setup properly, swiotlb buffer will be freed. The early allocating is with bootmem, and could panic when we try to use kdump with buffer above 4G only, or with memmap to limit mem under 4G. for example: memmap=4095M$1M to remove memory

Geting a seg fault. Have not investigted the cause. rkotler at mipsswbrd002:~/richard$ tar vfxz ~/Downloads/ellcc-mips-linux-2014-Mar-24-07-32-26.tgz rkotler at mipsswbrd002:~/richard/ellcc/bin$ gdb ./ecc GNU gdb (GDB) 7.4.1-debian Copyright (C) 2012 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html> This is free software: you are

Howdy, <this messages is cross posted in freebsd-security and freebsd-net> I'm seeking current cryptographic coprocessors supported in FreeBSD 8.x. By perusing through the crypto-dev (and subsequently referenced) man page(s) I found this list: Hifn 7751/7951/7811/7955/7956 crypto accelerator SafeNet 1141/1741 Bluesteel 5501/5601 Broadcom

Hi all, this series replaced the DMA_ATTR_NON_CONSISTENT flag to dma_alloc_attrs with a separate new dma_alloc_pages API, which is available on all platforms. In addition to cleaning up the convoluted code path, this ensures that other drivers that have asked for better support for non-coherent DMA to pages with incurring bounce buffering over can finally be properly supported. I'm still a

The term "target" is somewhat overloaded. When llvm-config tells you it was built with the X86 target, that actually includes a variety of closely related architectures, such as x86_64, i386, and so on. Within the x86_64 architecture, there are many individual processor implementations that LLVM understands, such as Skylake, Bulldozer, and many many more. What *clang* means by

- my old email address. The ISA_* classes might not be the best choice for this. There's an overall hierarchy and ordering to the ISA_* classes since they represent the generations of the MIPS ISA. If these extensions are available in Loongson chips based on MIPS32r1 and MIPS32r2 for example, it becomes difficult to describe with ISA_* classes without duplicating instruction definitions or

Hi, This is fifth approach for replacing struct dma_attrs with unsigned long. The main patch (1/44) doing the change is split into many subpatches for easier review (2-42). They should be squashed together when applying. Rebased on v4.7-rc5. For easier testing the patchset is available here: repo: https://github.com/krzk/linux branch: for-next/dma-attrs-const-v5 Changes since v4

I recently got a tegra TK1 and was curious how fast it was compared to my previous arm "build machine": the original arm Samsung chromebook. I timed running ninja to build just llvm in Release+Asserts using clang as the host compiler. chromebook: real 84m30.939s user 163m50.145s sys 4m0.100s TK1: real 34m7.376s user 132m44.417s sys 3m3.543s A really nice

On Thu, 2013-08-15 at 12:14 +0200, Pavel Machek wrote: > Hi! > Hi! > > > > Since it is a PCIe card, it does not have the ability to host hardware > > > > devices for networking, storage and console. We provide these devices > > > > on X100 coprocessors thus enabling a self-bootable equivalent environment > > > > for applications. A key

On Thu, 2013-08-15 at 12:14 +0200, Pavel Machek wrote: > Hi! > Hi! > > > > Since it is a PCIe card, it does not have the ability to host hardware > > > > devices for networking, storage and console. We provide these devices > > > > on X100 coprocessors thus enabling a self-bootable equivalent environment > > > > for applications. A key

While running a multiple VM testscase with each VM running iperf traffic between others the following kernel NULL pointer exception was seen. Race appears when the tun driver instance of one VM calls skb_array_produce (from tun_net_xmit) and the the destined VM's skb_array_consume (from tun_ring_recv), which could run concurrently on another core. Due to which the sock_wfree gets called again

While running a multiple VM testscase with each VM running iperf traffic between others the following kernel NULL pointer exception was seen. Race appears when the tun driver instance of one VM calls skb_array_produce (from tun_net_xmit) and the the destined VM's skb_array_consume (from tun_ring_recv), which could run concurrently on another core. Due to which the sock_wfree gets called again

Hi, Is there any information available on porting Syslinux to 64bit ARM? Specifically, I have a Cavium ThunderX board (Gigabyte R120-T30) which boots using UEFI - b2b.gigabyte.com/products/product-page.aspx?pid=5864#ov I'd be very interested in getting this to work, as currently the only option for booting on this platform is Grub 2 or EFI Stub. If anyone can point me in the right

On Tue, 2013-08-13 at 14:43 +0200, Pavel Machek wrote: > Hi! > > > Since it is a PCIe card, it does not have the ability to host hardware > > devices for networking, storage and console. We provide these devices > > on X100 coprocessors thus enabling a self-bootable equivalent environment > > for applications. A key benefit of our solution is that it leverages >

On Tue, 2013-08-13 at 14:43 +0200, Pavel Machek wrote: > Hi! > > > Since it is a PCIe card, it does not have the ability to host hardware > > devices for networking, storage and console. We provide these devices > > on X100 coprocessors thus enabling a self-bootable equivalent environment > > for applications. A key benefit of our solution is that it leverages >

Users of ptr_ring expect that it's safe to give the data structure a pointer and have it be available to consumers, but that actually requires an smb_wmb or a stronger barrier. In absence of such barriers and on architectures that reorder writes, consumer might read an un=initialized value from an skb pointer stored in the skb array. This was observed causing crashes. To fix, add memory

Users of ptr_ring expect that it's safe to give the data structure a pointer and have it be available to consumers, but that actually requires an smb_wmb or a stronger barrier. In absence of such barriers and on architectures that reorder writes, consumer might read an un=initialized value from an skb pointer stored in the skb array. This was observed causing crashes. To fix, add memory

I'm cross-compiling for MIPS. The test-case is as simple as it can be: void foo() {} $clang -target mips64-octeon-linux -c -B path/to/cross/compiled/mips/assembler a.c And then I look at the object file: $ nm a.o 0000000000000020 t $tmp0 0000000000000000 T foo I would like to know what "$tmp0" is. Furthermore, if I pass -g to clang, I see a whole bunch of such symbols. Some of