similar to: [LLVMdev] c-like language implementation using llvm

Hi Sean, >> Can I just utilize the i1 type? Is the >> i1 type already used for something, and thus might create a conflict? > > I think you are very confused. LLVM's types are meant to be used to > represent *your* program :) They can't be "already used". I am keeping all the types of C, and adding my new types. I thought that, for example, I can't map

> Can I just utilize the i1 type? Is the > i1 type already used for something, and thus might create a conflict? I think you are very confused. LLVM's types are meant to be used to represent *your* program :) They can't be "already used". > 2) Can I use LLVM's intrinsic functions for my gates, something like > @llvm.NOT(i1 %val)? Would the fact that the

On Sun, Feb 3, 2013 at 8:55 PM, Ali Javadi <aj14889 at yahoo.com> wrote: > I am keeping all the types of C, and adding my new types. I thought that, > for example, I can't map my new type to i32 because that's used for C > integers. That's what I meant by already used. Am I missing something? If the type behaves like an i32 then use i32. For example, both signed and

Hi there, I asked this a few days ago and Sean gave a useful answer. Going back to the second question below, I want to clarify something. On Feb 3, 2013, at 9:04 PM, Sean Silva <silvas at purdue.edu> wrote: > On Sun, Feb 3, 2013 at 8:55 PM, Ali Javadi <aj14889 at yahoo.com> wrote: >> I am keeping all the types of C, and adding my new types. I thought that, >> for

Hi, In my llvm code I want to create some function calls. The function prototype is as follows: int memoize ( char *function_name, int *int_params, unsigned num_ints, double *double_params, unsigned num_doubles) In order to create these calls I do the following for example: %88 = alloca [7 x i8] store volatile [7 x i8] c"ORACLE\00", [7 x i8]*

Stack colouring should be able to reuse the same stack space, if the live ranges of the pointers don't overlap. But I don't think anyone has built a general solution for alloca'd space. On Mon, Nov 4, 2013 at 6:30 AM, Ali Javadi <aj14889 at yahoo.com> wrote: > Hi, > > In my llvm code I want to create some function calls. The function > prototype is as follows: >

Dear Mr. Beginning to work on Linux. I am trying to install R into Ubuntu Gustsy. I installed version 2.5.1 and worked fine. But then I tried to upgrade by adding these lines to sources.list: deb http://cran.fiocruz.br/bin/linux/debian etch-cran/ deb http://cran.fiocruz.br/bin/linux/ubuntu gutsy/ I introduced the authorization keys (as recommended) and the files were downloaded. But then I

Hi, I have some newly defined intrinsic functions in my llvm IR code, which I want to translate to X86 instruction set. As a first step, I want to be able to generate "nop" for these instructions, so the program at least compiles successfully. The call to my intrinsic function looks like this in the IR: call void @llvm.X(i16 %43) >From what I understand it may be possible to

Hi, In LLVM (using the opt tool), is it possible to force a nested loop be unrolled entirely? Something like a pass option? I have a nested loop with depth of 4, and all trip counts are known at compile time, but so far I've only been able to do this by 4 invocations of the -loop-simplify, -loop-rotate, -loop-unroll passes. Thanks, Ali

On Sun, Apr 24, 2005 at 07:15:03PM +0800, Tzu-Chien Chiu wrote: > i'd like to know if there is any plan or existing work to add a Aho's > trig language like code generator generator? I'm not aware of either the trig language code generator nor any work to implement it in LLVM. > "...If you are starting a new port, we recommend that you write the > instruction

On Sun, 24 Apr 2005, Tzu-Chien Chiu wrote: > i'd like to know if there is any plan or existing work to add a Aho's > trig language like code generator generator? Trig is a code generator generator? Is there any documentation for it available anywhere? -Chris > "...If you are starting a new port, we recommend that you write the > instruction selector using the

Hi llvm-dev: Sorry for bothering at this mailing list, as I don't know where to ask. I'm learning LLVM and read the tutorials and found that there are tutorials for C++, C and Ocaml users. I recently found that there are D bindings for LLVM and it is feasible to write this tutorial in D. I'd like to take on this little project and translate the code to D, making changes where

i'd like to know if there is any plan or existing work to add a Aho's trig language like code generator generator? "...If you are starting a new port, we recommend that you write the instruction selector using the SelectionDAG infrastructure." any other things i should know before i write one? thank you.

On Mon, 25 Apr 2005, Tzu-Chien Chiu wrote: > http://portal.acm.org/citation.cfm?id=75700 Oh, tWig. :) Yes, tree pattern matching is exactly the direction we are heading. We are slowly making the code generators more and more automatically generated as time goes on. The SelectionDAG infrastructure is mean to support exactly this (perform Tree or DAG pattern matching on the optimized DAG

http://portal.acm.org/citation.cfm?id=75700 On 4/25/05, Chris Lattner <sabre at nondot.org> wrote: > On Sun, 24 Apr 2005, Tzu-Chien Chiu wrote: > > i'd like to know if there is any plan or existing work to add a Aho's > > trig language like code generator generator? > > Trig is a code generator generator? Is there any documentation for it > available

Hi, I am new to LLVM and I find TableGen language really cryptic. The reference manual to the language is not helpful either. I can look at the existing .td file and reverse engineer but I am looking for a detailed manual. Specifically, I have below questions: 1. What is a basic syntax for writing a dag? From the lang ref manual I can see that its something like operator followed by ArgList which

Hi, I'd like to get a rough idea on how much work it would be to port Samba to a non-unix platform. My plan was to use a slimmed-down samba to read and write files on a particularly unfriendly piece of proprietary hardware we use at work. I'm fine with a minimalistic samba as this port would be for internal, single-developer use and not intended for file serving in general. Here are some

Hey Sean, So the processor does in-memory computing, it reads instructions and operands from the memory array, performs the majority operations within the memory array itself. It does instructions using resistive majority which is AB'+B'C+AC Like it does AND operation as 1: 0, 1, @C; //C=0 2: 0, 1, @Binv; //Binv=0 3: 1, @B, @Binv; //Binv=B 4: @A, @Binv, @C; //C=A.B where each operation is

On Mon, 25 Apr 2005, Tzu-Chien Chiu wrote: > i'd like to know what progress you guys have made (not on cvs?). Everything is in CVS. Noone is currently working on automating the pattern matching generator process yet. Before doing that, there are a few changes we want to make to the SelectionDAG interface. In particular, right now, the selection process basically works like this: #1.

the proposed architecture (chris) doesn't seem to attack the phase ordering problem. through having independent instruction selection, instruction scheduling, and register allocation phases faciliate a modular design, but i believe the phase-coupled code generator generator high quality code on many architectures. espeically in the embedded system like a media/dsp processors with very limited