similar to: [LLVMdev] [PATCH] LLVM build failure on OpenBSD/mips64

On Mar 6, 2012, at 5:05 PM, Akira Hatanaka <ahatanak at gmail.com> wrote: > I am having trouble trying to enable post RA scheduler for the Mips backend. > > This is the bit code of the function I am compiling: > > (gdb) p MF.Fn->dump() > > define void @PointToHPoint(%struct.HPointStruct* noalias sret > %agg.result, %struct.ObjPointStruct* byval %P) nounwind {

I am having trouble trying to enable post RA scheduler for the Mips backend. This is the bit code of the function I am compiling: (gdb) p MF.Fn->dump() define void @PointToHPoint(%struct.HPointStruct* noalias sret %agg.result, %struct.ObjPointStruct* byval %P) nounwind { entry: %res = alloca %struct.HPointStruct, align 8 %x2 = bitcast %struct.ObjPointStruct* %P to double* %0 = load

On Mar 7, 2012, at 11:34 AM, Akira Hatanaka <ahatanak at gmail.com> wrote: > I filed a bug report (Bug 12205). > Please take a look when you have time. > > Per your suggestion, I also attached a patch which attaches to load or > store nodes a machinepointerinfo that points to a stack frame object > when it can infer they are actually reading from or writing to the >

I filed a bug report (Bug 12205). Please take a look when you have time. Per your suggestion, I also attached a patch which attaches to load or store nodes a machinepointerinfo that points to a stack frame object when it can infer they are actually reading from or writing to the stack. The test that was failing passes if I apply this patch, but I doubt this is the right approach, because this

Thank you for your suggestions. I implemented the first approach (provided the byval argument and offset to MachinePointerInfo) and it seems to have fixed the instruction ordering problem. It was a lot simpler than initially expected. In this particular case, is the user responsible for providing alias information to MachinePointerInfo to guarantee instructions are emitted in the correct order?

This patch is needed to allow klibc to be compiled on a mips compiler configured to use the FPXX ABI (which is in GCC 5). In that ABI the odd numbered FPU registers cannot be used directly, but they can be accessed using the double word sdc1 and ldc1 instructions. See this page for more info: https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking Signed-off-by: James Cowgill

Commit-ID: 59f3f33338f371b3a30163406fbb5fe323503939 Gitweb: http://git.kernel.org/?p=libs/klibc/klibc.git;a=commit;h=59f3f33338f371b3a30163406fbb5fe323503939 Author: James Cowgill <james.cowgill at mips.com> AuthorDate: Fri, 2 Mar 2018 08:33:02 -0800 Committer: Ben Hutchings <ben at decadent.org.uk> CommitDate: Wed, 2 Jan 2019 03:08:04 +0000 [klibc] mips/mips64: simplify

Hi all, When compiling some programs using the Mips backend i'm getting this assert message on lib/CodeGen/LiveInterval.cpp:227: "Range is not entirely in interval!" I don't know yet if it's something that is missing on the backend code or why the range to be removed it outside the interval, does anyone have any clue? A more detailed output is attached. The program i tried

On 19/08/2009, at 4:00 AM, Anton Korobeynikov wrote: > Hello, Nathan > >> or if it should be a configure test, which might be safer. Are there >> any x86 platforms (other than apple) that don't need PLT-indirect >> calls? > Yes, mingw. However just tweaking the define is not enough - we're not Ok, so configure might be the way to go then, maybe something

Does it make a difference if you give the "-target" option to clang? $ clang -target mips-linux-gnu ch8_3.cpp -o ch8_3.bc -emit-llvm -c The .s file generated this way looks quite different from the one in your email. On Tue, Feb 19, 2013 at 5:06 PM, Jonathan <gamma_chen at yahoo.com.tw> wrote: > I didn't have Mips board. I compile as the commands and check the asm >

I didn't have Mips board. I compile as the commands and check the asm output as below. 1. Question: The distance of caller arg[4] and arg[5] is 4 bytes. But the the callee get every arg[] by 8 bytes offset (arg_ptr1+8 or arg_ptr2+8). I assume the #BB#4 and #BB#5 are the arg_ptr which is the pointer to access the stack arguments. 2. Question: Stack memory 28($sp) has no initial value. If

i have this code typedef long long L; typedef integer I; void test2(auto L p0, auto L p1, auto L p2, auto L p4, ...) { va_list select; va_start (select, p4); report( va_arg(select,L) ); report( va_arg(select,I) ); report( va_arg(select,L) );

Hi Rafael, Sure, the expansion of at least .cpload should be done in the Target ELFStreamer but AFAICS it doesn't solve my initial problem. MCCodeGenInfo is not created in tools where CodeGen isn't needed (llvm-mc) and it's still not possible to access the Relocation Model in MCObjectFileInfo from the target streamer (private member). Am I missing something obvious ? There are many

Could you file a bug? On Wed, Feb 27, 2013 at 2:47 AM, Stavropoulos Nikos < n.stavropoulos at think-silicon.com> wrote: > i have this code > > typedef long long L; > typedef integer I; > void test2(auto L p0, auto L p1, auto L p2, auto L p4, ...) > { > va_list select; > > va_start (select, p4); > > report( va_arg(select,L) ); > report(

Hi, I am hoping that someone can help me figure out how to prevent the insertion of "memcpy" from the assembly source. My target is an instruction set simulator that doesn't support this. Thank you for your valuable time. Wolf *Here are my compile commands:* $ clang -emit-llvm -fno-builtin -o3 --target=mips -S matrix_float.c -o vl_matrix_float.ll $ llc vl_matrix_float.ll *IR

Sorry if this is a duplicate: I tried to send it last night and it didn't go through. I'm trimming some text to see if it helps. I have a simple program that fails on the Microblaze: int main() { unsigned long long x, y; x = 100; y = 0x8000000000000000ULL; return !(x > y); } As you can see, the test case compares two unsigned long long values. To try to track

Some Mips macros (e.g. la[1]) and the handling of Mips directives used for Position-Independent Programming (e.g. .cpload[2]) require access to Reloc::Model from within the Assembly Parser but there doesn't seem to be a way to do it in its current form. 1) Reloc::Model is passed to MCObjectFileInfo but it's a private member of that class 2) TargetMachine is not accessible I can also

Hi Reed, Still catching up on email, so hope this isn't already covered... reed kotler <rkotler at mips.com> writes: > I have a strange issue that I encountered with mips16 hard float. > > Part of mips16 hard float is to emit calls to runtime routines with the > same signature as usual soft float routines, except that they are > implemented using mips32 code which uses

From: Dejan Latinovic <Dejan.Latinovic at imgtec.com> --- usr/include/arch/mips64/klibc/archconfig.h | 3 + usr/include/arch/mips64/klibc/archsetjmp.h | 39 ++++++ usr/include/arch/mips64/machine/asm.h | 76 ++++++++++ usr/include/fcntl.h | 2 +- usr/include/sys/md.h | 1 + usr/include/sys/resource.h | 4 +-

Alright, couple of points here: 1. Address space 0 is invalid for global variables. This is causing a crash in llc where we use llvm_unreachable() on this case. This is most likely why you're seeing llc run forever. The fix for this is to use address space 1 for globals, which puts them into PTX global memory. On our side, we should provide a meaningful error message in this case. 2. The