similar to: [LLVMdev] Issue with instruction decoding / disassembly

Displaying 20 results from an estimated 500 matches similar to: "[LLVMdev] Issue with instruction decoding / disassembly"

2012 Dec 18
0
[LLVMdev] Issue with instruction decoding / disassembly
Owen, As I recall, we had some similar issues with custom decoders needing to cooperate on ARM. Do you remember the details? -Jim On Dec 18, 2012, at 2:37 AM, Richard Osborne <richard at xmos.com> wrote: > I'm currently trying to get llvm-mc --disassemble working for the XCore backend. Up until recently there was no instruction encoding / decoding information on any of the XCore
2014 Jul 09
2
[LLVMdev] How to resolve decoding conflict?
Hi all, Short version I get decoding conflicts during generation of disassembler tables for my modified PowerPC backend: 001100.......................... ................................ ADDIC 001100__________________________ E_LBZ 001100__________________________ Which methods can be used to resolve this kind of error? Long version: I'm trying to implement support for the PowerPC
2014 Nov 03
2
[LLVMdev] Mips's MicroMips ??
Hello Daniel, At the moment we are preparing the patch for disassembling microMIPS 16 bit instructions and it will be on Phabricator tomorrow or on Wednesday. Functionality is implemented in MipsDisassembler::getInstruction where first two bytes are read and decodeInstruction is called with DecoderTableMicroMips16 and only if it fails we read 4 bytes and call decodeInstruction with
2015 Feb 27
2
[LLVMdev] LLVM register number for MIPS DAGToDAG
Is it possible to get a register number to which the value is allocated to in MIPS in DAGToDAG class? More Specifically: SDValue Reg3 = Node->getOperand(3); if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Reg3)) { op3 = cast<RegisterSDNode>(Reg3)->getReg();
2012 Sep 29
1
Error during decryption of meta key
Hi, I've got a relatively simple tinc setup. I've got two "servers" that are on the public internet that act as routers for three "clients" that are behind NATs. Those servers are called aaaaa and bbbbb the clients are xxxxx, yyyyy and zzzzz Unfortunatly the servers have problems accepting a connection from the clients syslog on aaaaa: Sep 29 18:28:58 schuerrer
2007 Jun 29
2
connection dropped by imap
hello, when i create imap account in mail client (ex: outlook, thunderbird) it's allright. but if i want login with this account to webmail (i have 2 webmail: squirrelmail and roundcube) commonly i get error. squirrelmail say: Connection droped by imap. roundcube say nothing(white screen). But sometimes i can login. and i see one thing... when i restart apache, i can login above 1-2 hours,
2015 Feb 27
0
[LLVMdev] LLVM register number for MIPS DAGToDAG
> On Feb 27, 2015, at 1:59 AM, Ambuj Agrawal <ambujbwt at gmail.com> wrote: > > Is it possible to get a register number to which the value is allocated to in MIPS in DAGToDAG class? > > More Specifically: > SDValue Reg3 = Node->getOperand(3); > if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Reg3)) >
2010 Sep 29
2
[LLVMdev] comparison pattern trouble
Our architecture has 1-bit boolean predicate registers. I've defined comparison def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; But then I end up having the following bug: Code %0 = zext i8 %data to i32 %1 = zext i16 %crc to i32 %2 = xor i32 %1, %0 %3 = and i32 %2, 1 %4 =
2015 Feb 28
2
[LLVMdev] LLVM register number for MIPS DAGToDAG
Thanks for your reply Quentin. I do understand that the registers are allocated much later in the pipeline. I am assuming that the physical registers are allocated before MipsAsmPrinter class. I am doing something like if (MI->getOpcode() == Mips::OPCODE) { unsigned n = MI->getNumOperands(); for(unsigned i=0 ; i < n ; i++) { const MachineOperand &MO =
2011 May 07
3
how to not match partial names
Dear friends, How do I stop partial matching of list names? e.g., x <- list(AAAA="aaaaa", BBBBB="bbbbb") is.null(x$A) #returns FALSE even though there is no element A. if(is.null(x$A)) {result <- x$BBBB} else {result <- x$A} result #is aaaa even though there is no x$A element x <- list(CCCC="aaaaa", BBBBB="bbbbb") if(is.null(x$A))
2015 Feb 13
4
Centos 6 Sendmail backup MX Config
Hi All, I'm just wanting to check that my understanding of the settings is correct as my web searches are finding a lot of dated information. If I want a Centos 6 sendmail system act as the secondary MX for domain bbbbb.co.uk do I just add a Connect:bbbbb.co.uk RELAY statement into /etc/mail/access and restart sendmail Obviously I have the DNS MX records for the domain are
2015 Oct 24
4
ADUC - "UNIX Attributes" tab - "Unwilling To Perform"
Thanks Rowland - appreciated. I have checked the ldbsearch result and both groups look to be pretty much exactly the same to me, one of them is shown below (I have sanitised some of the output, replacing parts with 123/a/b/c, but the rest of the output is byte for byte as seen) In the time between posting my original message and checking again just now, however, I have the following additional
2013 Feb 15
10
reading data
Hi, #working directory data1 #changed name data to data1.? Added some files in each of sub directories a1, a2, etc. ?indx1<- indx[indx!=""] lapply(indx1,function(x) list.files(x)) #[[1]] #[1] "a1.txt"??????? "mmmmm11kk.txt" #[[2]] #[1] "a2.txt"??????? "mmmmm11kk.txt" #[[3]] #[1] "a3.txt"??????? "mmmmm11kk.txt" #[[4]] #[1]
2010 Sep 29
1
[LLVMdev] comparison pattern trouble - might be a bug in LLVM 2.8?
On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > Our architecture has 1-bit boolean predicate registers. > > I've defined comparison > > > def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; > > > > > But then I end up having the following bug: > >
2014 Oct 29
2
[LLVMdev] Mips's MicroMips ??
Hi, We have this line in micromips-16-bit-instructions.s # CHECK-EB: addu16 $6, $17, $4 # encoding: [0x07,0x42] However, when I check this with llvm-mc, like below, I dont get back the assembly. This is against the latest LLVM code. What is wrong here? Thanks, Jun $ echo "0x07,0x42"|./Release+Asserts/bin/llvm-mc -disassemble -triple=mips -show-encoding -mattr=micromips
2015 Oct 23
2
ADUC - "UNIX Attributes" tab - "Unwilling To Perform"
Hi, I am sure I have come across this before but have previously either ignored it or somehow worked around it. However it has come up again and this time I will try to find out what's going on, hopefully we can fix whatever the issue is. I have a Samba 4.2.2 domain that generally works fine; I have rfc2307 enabled so that I can keep UIDs/GIDs consistent across machines whilst still being
2015 Mar 09
2
[LLVMdev] LLVM Backend DAGToDAGISel INTRINSIC
I am currently working on DAGToDAGISel class for MIPS and am trying to figure out a way to use INTRINSIC_W_CHAIN for an intrinsic which can return a value. My intrinsic is defined as: Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],[IntrReadWriteArgMem]>; i.e. it has four arguments and one return value In DAGToDAGISel when I try to pass it with four arguments and
2020 Aug 25
3
[TableGen] What to do if there are overlapping instruction patterns?
I've been working on adding support for a (semi-proprietary) extension for PowerPC called "Paired-Singles". It's a SIMD instruction set supporting various operations on a vector of 2 32-bit floating point numbers. The Extension is found in the PowerPC 750CL, modified variants of it are used in the Nintendo GameCube (Gekko), the Nintendo Wii (Broadway) and the Nintendo Wii U
2010 Sep 30
4
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
Bill Wendling wrote: > On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > >> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >> >>> Our architecture has 1-bit boolean predicate registers. >>> >>> I've defined comparison >>> >>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set
2010 Oct 01
2
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
On 1 Oct 2010, at 13:35, Bill Wendling wrote: > On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote: > >> Bill Wendling wrote: >>> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: >>> >>>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >>>> >>>>> Our architecture has 1-bit boolean predicate registers. >>>>>