similar to: [LLVMdev] Compile code for arm

On 8 December 2012 19:10, Amir Yazdanbakhsh <amir.yazdanbakhsh at gmail.com> wrote: > Hi, > > I've installed clang version 3.3 on ubuntu. > I want to cross-compile a C code into ARM (preferably) ARMv7. I want to get > both assembly code and binary. Can anyone help me what are the steps which > should I take? clang -triple arm-none-eabi (or many other variations

Thanks for your help. But I got this warning which it seems it doesn't use -triple "clang: warning: argument unused during compilation: '-triple arm-none-eabi' " Best Regards, A. Yazdanbakhsh >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> PhD. Student School of

Ok, These are the three options you should be playing with: -ccc-host-triple $(CCC_HOST_TRIPLE_ARM) \ --sysroot=$(SYSROOT_ARM) \ -gcc-toolchain $(GCC_TOOLCHAIN) Where the (sic) host triple defines the "target" triple too. Sysroot and gcc-toolchain is where you'll find the libraries and binutils for the ARM targets (you'll need them, since LLVM still can't cross-compile on

OK. Thanks for your help. My problem is I am playing with the size of registerfile in ARM. I thought I can do it with only modifying the Target in the LLVM directory. But if it is going to use gcc-toolchain, then I need to modify them as well which is a huge work! Best Regards, A. Yazdanbakhsh

Thanks Tim. I just need the assembly file. Anyway, I still have problem with generating assembly for the ARM without having any thumb and other fancy instructions. Best Regards, A. Yazdanbakhsh >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> PhD. Student School of Electrical and Computer

Hi Amir, On Dec 8, 2012 8:13 PM, "Amir Yazdanbakhsh" <amir.yazdanbakhsh at gmail.com> wrote: > My problem is I am playing with the size of registerfile in ARM. I thought I can do it with only modifying the Target in the LLVM directory. But if it is going to use gcc-toolchain, then I need to modify them as well which is a huge work! That sort of depends how you modify it. If

Hi, I want to increase the number of integer registers in the ARM machine. I don't have any idea how/where I can start. Can anybody help me? By the way, what are the following line in the ARMRegisterInfo.td specify: def qsub_0 def qsub_1 .... Thanks Best Regards, A. Yazdanbakhsh

Hi All, I am working to cross compile (just generate assembly code) a simple C code in ARM. First, I use CLANG to get LLVM bytecode, then I use llc to generate assembly for ARM. The problem is it never uses any other register except r0-r3 and always uses spill code even if other register are available to use. Anyone has any idea? Thanks Best Regards, A. Yazdanbakhsh

Hello, clang/llvm 4.0.0 generates invalid calls for builtin functions with -mfloat-abi=hard -ffast-math. Small example fail.c: // clang -O2 -target armv7a-none-none-eabi -mfloat-abi=hard -ffast-math -S fail.c -o - extern float sinf (float x); float sin1 (float x) {return (sinf (x));} generates code to pass the parameter in r0 and expect the result in r0. The same code without

Hi Renato, On 06/25/12 12:13 AM, Renato Golin wrote: > Hi Karel, > > I understand this patch has already been merged (to 3.0), so don't > take my question as stopping the merge to head, I'm just making sure I > got it right... The rest looks correct. > > + CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, > + CCIfType<[f64], CCAssignToReg<[D8, D9,

I noticed that LLD doesn’t preserve the symbol type for a defsym directive. For example: $ cat f.c void f() {} $ clang -c f.c $ ld.lld -shared --defsym=g=f f.o $ objdump -T a.out DYNAMIC SYMBOL TABLE: 00000000000012a0 g DF .text 0000000000000006 f 00000000000012a0 g D .text 0000000000000000 g f is marked as a function symbol, but g is not. I recognize this is hard to do in the general

I almost change all the instruction formats. It was a huge work. I am going to compile and run it now. Best Regards, A. Yazdanbakhsh >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> PhD. Student School of Electrical and Computer Engineering University of Wisconsin-Madison E-mail: yazdanbakhsh

On 29 June 2012 17:46, Karel Gardas <karel.gardas at centrum.cz> wrote: > Yes and no. Shortly: original GHC/ARM/LLVM port was done by Stephen on > ARMv5/Qemu IIRC. I've later added whole VFP support and ARMv7 support. The > code in GHC is properly #ifdefed, so if there is no VFP available on pre > ARMv6, then it's not used. ie. GHC STG floating points regs are then >

Hi I would like to use clang to cross compile the ARM binary. I hope the target binary contains both arm and thumb instruction sets. I use the flag -mhwdiv=arm,thumb. I compiled several binaries. However, I found that the thumb mode instructions are few. Even for very big program like gcc. The number of thumb mode instruction is less than 100. I get the ground truth from the mapping table.

On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote: > The code below in lib/Target/ARM/ARMRegisterInfo.td is where you > should look into, > > // Integer registers > def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>; > def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>; > > ... That's the easy part. ARM (AArch32) has 16 registers

On Wed, Dec 05, 2012 at 09:17:12PM -0600, Amir Yazdanbakhsh wrote: > Hi, > > I want to increase the number of integer registers in the ARM machine. > I don't have any idea how/where I can start. Can anybody help me? The code below in lib/Target/ARM/ARMRegisterInfo.td is where you should look into, // Integer registers def R0 : ARMReg< 0, "r0">,

On Thu, Dec 06, 2012 at 09:13:53AM +0000, David Chisnall wrote: > On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote: > > > The code below in lib/Target/ARM/ARMRegisterInfo.td is where you > > should look into, > > > > // Integer registers > > def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>; > > def R1 : ARMReg< 1,

I used your code and it works fine. Once I increase the number of variable it uses the extra registers which I added. I have another problem. To generate the assembly file for new ARM machine with extra registers,I follow these steps: 1) clang -emit-llvm main.ll main.c 2) llc -march=arm -o main.s main.bc In this case it doesn't use the registers which I added to the architecture. Do you

Motivation At the moment, when targeting armv7a, clang defaults to generate code as if -mcpu=cortex-a8 was specified. When targeting armv8a, it defaults to generate code as if -mcpu=cortex-a53 was specified. This leads to surprising code generation, by the compiler optimizing for a specific micro-architecture, whereas the intent from the user was probably to generate code that is

On Sun, Dec 9, 2012 at 7:48 PM, Evan Cheng <evan.cheng at apple.com> wrote: > Sound like you are not enabling optimization. Try with -O3. Ah, of course! I'd forgotten about the extra allocas produced by clang. To expand a little, the spills you're seeing are (probably) specifically created by clang (it creates a shadow variable for each local with alloca). "llc" on its