similar to: [LLVMdev] Increase the number of registers in ARM

On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote: > The code below in lib/Target/ARM/ARMRegisterInfo.td is where you > should look into, > > // Integer registers > def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>; > def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>; > > ... That's the easy part. ARM (AArch32) has 16 registers

On Thu, Dec 06, 2012 at 09:13:53AM +0000, David Chisnall wrote: > On 6 Dec 2012, at 07:46, 陳韋任 (Wei-Ren Chen) wrote: > > > The code below in lib/Target/ARM/ARMRegisterInfo.td is where you > > should look into, > > > > // Integer registers > > def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>; > > def R1 : ARMReg< 1,

On Wed, Dec 05, 2012 at 09:17:12PM -0600, Amir Yazdanbakhsh wrote: > Hi, > > I want to increase the number of integer registers in the ARM machine. > I don't have any idea how/where I can start. Can anybody help me? The code below in lib/Target/ARM/ARMRegisterInfo.td is where you should look into, // Integer registers def R0 : ARMReg< 0, "r0">,

I almost change all the instruction formats. It was a huge work. I am going to compile and run it now. Best Regards, A. Yazdanbakhsh >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> PhD. Student School of Electrical and Computer Engineering University of Wisconsin-Madison E-mail: yazdanbakhsh

Hi folks, TableGen provides sufficiently rich syntax for expressing target instruction set. Nevertheless, when I wrote the PTX backend, I observed that some redundancy in TableGen can be further eliminated through macro expansion of for-loops. The semantics of a for-loop is expanding the for-loop body, and so it is equivalent to manually unroll the loop (see example #1). I believe the for-loop

Ok, These are the three options you should be playing with: -ccc-host-triple $(CCC_HOST_TRIPLE_ARM) \ --sysroot=$(SYSROOT_ARM) \ -gcc-toolchain $(GCC_TOOLCHAIN) Where the (sic) host triple defines the "target" triple too. Sysroot and gcc-toolchain is where you'll find the libraries and binutils for the ARM targets (you'll need them, since LLVM still can't cross-compile on

OK. Thanks for your help. My problem is I am playing with the size of registerfile in ARM. I thought I can do it with only modifying the Target in the LLVM directory. But if it is going to use gcc-toolchain, then I need to modify them as well which is a huge work! Best Regards, A. Yazdanbakhsh

Thanks for your help. But I got this warning which it seems it doesn't use -triple "clang: warning: argument unused during compilation: '-triple arm-none-eabi' " Best Regards, A. Yazdanbakhsh >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> PhD. Student School of

Thanks Tim. I just need the assembly file. Anyway, I still have problem with generating assembly for the ARM without having any thumb and other fancy instructions. Best Regards, A. Yazdanbakhsh >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> PhD. Student School of Electrical and Computer

Hi, I've installed clang version 3.3 on ubuntu. I want to cross-compile a C code into ARM (preferably) ARMv7. I want to get both assembly code and binary. Can anyone help me what are the steps which should I take? Second question, Is there anyway to tell compiler not to use any Thumb/NEON/VFP instructions? Thanks Best Regards, A. Yazdanbakhsh

On 8 December 2012 19:10, Amir Yazdanbakhsh <amir.yazdanbakhsh at gmail.com> wrote: > Hi, > > I've installed clang version 3.3 on ubuntu. > I want to cross-compile a C code into ARM (preferably) ARMv7. I want to get > both assembly code and binary. Can anyone help me what are the steps which > should I take? clang -triple arm-none-eabi (or many other variations

Hi Amir, On Dec 8, 2012 8:13 PM, "Amir Yazdanbakhsh" <amir.yazdanbakhsh at gmail.com> wrote: > My problem is I am playing with the size of registerfile in ARM. I thought I can do it with only modifying the Target in the LLVM directory. But if it is going to use gcc-toolchain, then I need to modify them as well which is a huge work! That sort of depends how you modify it. If

Hi All, I am working to cross compile (just generate assembly code) a simple C code in ARM. First, I use CLANG to get LLVM bytecode, then I use llc to generate assembly for ARM. The problem is it never uses any other register except r0-r3 and always uses spill code even if other register are available to use. Anyone has any idea? Thanks Best Regards, A. Yazdanbakhsh

> I almost change all the instruction formats. It was a huge work. I am going > to compile and run it now. We have done the similar work[1] on this topic by gcc and we have start migrate our platform to LLVM. In my experience, you need to take care the follow part: * ARMBaseRegisterInfo::getRegPressureLimit * ARMBaseRegisterInfo::getRawAllocationOrder * CalleeSavedRegs *

On Jan 9, 2012, at 10:00 AM, Jakob Stoklund Olesen wrote: > > On Jan 8, 2012, at 11:18 PM, Demikhovsky, Elena wrote: > >> I'll explain what we see in the code. >> 1. The caller saves XMM registers across the call if needed (according to DEFS definition). >> YMMs are not in the set, so caller does not take care. > > This is not how the register allocator

This is the wrong code: declare <16 x float> @foo(<16 x float>) define <16 x float> @test(<16 x float> %x, <16 x float> %y) nounwind { entry: %x1 = fadd <16 x float> %x, %y %call = call <16 x float> @foo(<16 x float> %x1) nounwind %y1 = fsub <16 x float> %call, %y ret <16 x float> %y1 } ./llc -mattr=+avx

Here's the PDF version. On Thu, 2006-11-16 at 20:50 -0800, Chris Lattner wrote: > On Fri, 17 Nov 2006, [ks_c_5601-1987] "̽" wrote: > > > > The attached document contains the present issues I met while developing > > a LLVM backend emits text assembly code for a new architecture. Most of > > them are problems should be resolved. > > I sincerely ask

Hi Chris, Chris Lattner wrote: >> 2) Line 369 of PPCInstrInfo.td, we declare the non-callee saved registers. >> However, Linux and Darwin do not have the same set >> of non-callee saved registers. I don't know how to make the if(isDarwin) test >> in here >> > > Take a look at ARM/ARMRegisterInfo.td for an example of this I tried to define Defs just

On Sep 3, 2010, at 10:46 AM, Jeff Kunkel wrote: > It's not too much of a problem then. I can make a DenseMap between the registers and my registers. It's just one more intermediate step for a lookup. > > I wish to mimic all the of the registers on the machine with my std::vector<RegisterInfo> RegisterIndexes; vector. Then when a register is used I can assign it easily. I

On Fri, 2 Feb 2007, Nicolas Geoffray wrote: > I have almost completed the implementation of a linux/ppc backend in llvm. Cool! > There were a few things to modify in > lib/Target/PowerPC with a lot of "if (!isDarwin)". Some meta comments: 1. Please don't change PPC -> llvmPPC. I assume that you did this because PPC is a #define in some system header. Please