similar to: [LLVMdev] Tracing C conditions to assembly branches

# Summary As a consequence of comparing the RISC-V LLVM MC assembler to the RISC-V GNU assembler I've noticed that a number of targets have quite different handling for pc-relative jumps/branches with immediate integer operands in llvm-mc vs GNU as. I'll admit that this isn't likely to occur in hand-written code (as you'd almost always prefer to use a label), but thought it was

Hello! This is Kernel 2.4.6-ac1 with ext3-0.8.0 compiled with cvs-gcc version 3.1 20010616 on alpha ev4. I have prepared one ext3 filesystem to play with. When my rc-scripts call mount -a during boot I receive this: Jul 6 22:01:30 Marvin kernel: Bad unaligned kernel access at fffffc0000883f54: fffffc00063f2e6e 2a 2 and the mount of this filesystem fails. A subsequent manual second try to

On Sun, 22 Apr 2007, Christopher Lamb wrote: > I have a back end which has both scalar and vector registers that > alias each other. I'm having a problem generating the ISel from > tablegen that appears only when a vector register class is declared > to contain integer vectors. At that moment tablegen doesn't seem to > be able to infer integer types in patterns that it was

I have a back end which has both scalar and vector registers that alias each other. I'm having a problem generating the ISel from tablegen that appears only when a vector register class is declared to contain integer vectors. At that moment tablegen doesn't seem to be able to infer integer types in patterns that it was able to before, but I'm not clear on why that's the

On Apr 23, 2007, at 5:06 PM, Chris Lattner wrote: > On Sun, 22 Apr 2007, Christopher Lamb wrote: >> I have a back end which has both scalar and vector registers that >> alias each other. I'm having a problem generating the ISel from >> tablegen that appears only when a vector register class is declared >> to contain integer vectors. At that moment tablegen

- Use MAC16_16 macros instead of (sum += a*b) and unroll a loop by 2. It increase performance when using optimized macros (ex: ARMv5E). A possible side effect of loop unroll is that i don't check for odd length here. - Add NEON version of FIR filter and autocorr -- Aur?lien Zanelli Parrot SA 174, quai de Jemmapes 75010 Paris France -------------- next part -------------- diff --git

Digging deeper... 1. Is there a good reason that v2f32 types are excluded from the isFloatingPoint filter? Looks like a bug to me. v2f32 = 22, // 2 x f32 v4f32 = 23, // 4 x f32 <== start ?? v2f64 = 24, // 2 x f64 <== end static inline bool isFloatingPoint(ValueType VT) { return (VT >= f32 && VT <= f128) || (VT

Hello Leslie, The errors coming from the gnu assembler are due to the file being assembled in Arm state, to get rid of the errors you'll either need to put a .thumb directive in the file, or pass -mthumb to the assembler via arm-linux-gnu-gcc -Wa,-mthumb (I think). I'm not able to explain what you are seeing in your print out as it doesn't quite match the map file. Looking at your

Please ignore my previous mail and patch, there is a new version :). Patch changes are: - Use MAC16_16 macros instead of (sum += a*b) and unroll a loop by 2. It increase performance when using optimized macros (ex: ARMv5E). A possible side effect of loop unroll is that i don't check for odd length here. - Add NEON version of FIR filter and autocorr - Add a section in autoconf in order to

arm: implement exception and hypercall entries. xen/arch/arm/xen/Makefile | 3 + xen/arch/arm/xen/asm-offsets.c | 61 ++++++++ xen/arch/arm/xen/entry.S | 596 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/xen/hypercalls.S | 67 +++++++++ xen/arch/arm/xen/physdev.c | 41 +++++ 5 files changed, 768 insertions(+), 0

Hello Leslie, I don't know quite what to say as I don't know precisely what your question is? If I am not being precise enough please can you put some explicit questions in? From what I can see in the output, here are some comments. >From your arc mapfiles it looks like that in the output both linker's have given the .text output section the correct base address given the

I am considering using MipsInstPrinter::printAliasInstr, which is auto-generated in MipsGenAsmWriter.inc, to print assembly idioms defined as instruction aliases. For example, an instruction which used to be printed as "nor $1, $2, $zero" can be printed as "not $1, $2" This is nice because it makes the code printed by code-gen or disassembler more readable. However, the

Howdy, <---stuff deleted -----> Basically the architecture I want to compile to (SABRE) RISC does not support a conditional branch or a select instruction. It supports explicit branches of the form. blt %a, %b, imm // branch on less than iff %a < %b then pc = pc + imm So there are various branch instructions like .... ble, beq, bne, blt, bltu and bleu (unsigned) Im just

Is LiveVariables updated correctly when TII->RemoveBranch and TII->InsertBranch are called in the following piece of code? - MachineBasicBlock::updateTerminator() line 307 of MachineBasicBlock.cpp: if (FBB) { // The block has a non-fallthrough conditional branch. If one of its // successors is its layout successor, rewrite it to a fallthrough // conditional branch.

Hi everyone, i?m a new user of R and i?m trying to translate an linear optimization problem from Matlab into r. The matlab code is as follow: options = optimset('Diagnostics','on'); [x fval exitflag] = linprog(f,A,b,Aeq,beq,lb,ub,[],options); exitflag fval x=round(x); Where: f = Linear objective function vector (vector of 45,rows) A = Matrix for linear inequality

On Mar 16, 2006, at 8:47 PM, Chris Lattner wrote: > On Thu, 16 Mar 2006, Eric Kidd wrote: >> The duplicate loads appear at the top of the %regex6 and %regex2 >> blocks below. I've tried various alias analysis implementations >> either alone or in combination. > > LICM doesn't remove common subexpressions, also -load-vn doesn't > affect LICM. Try

Hi all, In RISC-V ISA, the range of conditional branches is within 4KiB. In current implementation, if the branch target is out of range, LLVM MC will issue an error message to tell users it could not resolve the fixup record. I have compared the result with the GNU assembler. GNU assembler will convert the branch to inverted one plus jump to make the branch possible. The range of unconditional

> On Sep 13, 2017, at 9:03 PM, jin chuan see via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi All, > > Thanks for the reply. I managed to identify and fixed a few errors in my implementation. > > However, there are a few errors that i am not sure what is it indicating. > For starters, i think i should explain what i am trying to achieve. > > I am

Hi Guys, I''m trying to figure out a way to get a list of files with objects present on an OST that is down. Normally one could do: lfs find -O <OST> dir but that is giving us Input/output errors (I assume because the OST is down). Is there a good way to get a list of objects (Maybe from the MDS?), what OSTs they are on, and correlate them with files? Thanks, Mark -- Mark

From: Jyri Sarha <jsarha at ti.com> Semantics of inner_product_single have also been changed to contain the final right shift and saturation so it can also be implemented in the optimal way for the used platform. This change affects fixed point calculations only. I also added a new fixed point macro SATURATE32PSHR(x, shift, a). It does pretty much the same thing as SATURATE32(PSHR32(x,