Displaying 20 results from an estimated 30000 matches similar to: "[LLVMdev] How to get Function object in LLVM Pass"
2013 Mar 14
0
[LLVMdev] Get underlying object for Machine level memory operation
You can use the GetUnderlyingObjects function (notice the S at the end of the name) to collect zero or more underlying objects. This method is similar to GetUnderlyingObject except that it can look through phi and select instructions and return multiple objects.
On Mar 14, 2013, at 4:15 AM, rahul <rahul3527 at gmail.com> wrote:
> Hi,
>
> I am writing a pass that works at
2013 Mar 14
2
[LLVMdev] Get underlying object for Machine level memory operation
Hi,
I am writing a pass that works at machine level and runs as last pass in
llc (just before converting llvm specific machine instructions into target
specific instructions)
In this pass I am trying to get underlying object for memory operations.
It turns out that due to various optimizations on machine instructions, the
memory operand in the operation is not always getelementptr (for e.g., it
2013 Mar 15
2
[LLVMdev] Dependence Analysis on Machine code
Hi,
I am trying to do dependence analysis (loop dependences) on machine code.
But, scalar evolution doesn't work as expected (like at IR level - opt
pass).
I am not getting enough clue as to how to proceed..
One naive way of getting the dependence information can be
- Do dependence analysis at IR level and attach the information as meta
data.
And then use this information at machine code
2013 Mar 18
0
[LLVMdev] Dependence Analysis on Machine code
On Mar 15, 2013, at 3:18 AM, rahul <rahul3527 at gmail.com> wrote:
>
> Hi,
>
> I am trying to do dependence analysis (loop dependences) on machine code.
> But, scalar evolution doesn't work as expected (like at IR level - opt pass).
> I am not getting enough clue as to how to proceed..
>
> One naive way of getting the dependence information can be
> - Do
2013 Mar 11
1
[LLVMdev] AESOP autoparallelizing compiler
Hi Rahul,
Thanks for your interest!
Our work does not attempt to make any significant contributions to alias analysis, and acts as a client to existing LLVM AA. Furthermore, the options passed to the AESOP frontend scripts are obeyed at compile time, but at link time certain transformations occur unconditionally.
Here, AESOP has actually thwarted your experiment by performing inlining just
2013 Mar 11
0
[LLVMdev] AESOP autoparallelizing compiler
Hi Timothy,
Today I happened to download the code and do some experiments.
I actually wanted to see how you handle inter-procedure alias analysis.
So, I set inline threshold to zero and tried out following example
===============================================
#define N 1024
void func(double *A, double *B)
{
int i;
for (i=1; i<N-2; i++) {
B[i] = A[i] + i*3;
}
}
void func1(double
2013 Mar 15
0
[LLVMdev] Problems about developing LLVM pass on windows visual studio
I just want to know ,how can I developing a LLVM Pass on Windows' visual
studio?
I can develop a Pass on linux,but I can't do it on windows.
2013/3/15 <llvmdev-request at cs.uiuc.edu>
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2012 Jul 26
2
Passing arguments to SQL Query in R
Hello all,
I am a newbie at R, with some experience in PERL.
I have a database table that contains the following data:
Name | Score
======= | =====
Sachin T | 25
Sachin T | 53
Sachin T | 57
Sachin T | 34
Rahul D | 38
Rahul D | 31
Rahul D | 53
Ricky P | 7
Ricky P | 45
Ricky P | 27
Ricky P | 17
Ricky P | 86
Ricky P | 48
Jacques K | 23
Jacques K | 86
Jacques K | 32
I
2012 Jul 31
1
[LLVMdev] ARM JIT support status?
Hi Rahul,
I believe that ARM support is working in the MCJIT engine (as of llvm 3.1). If it wasn't working in the legacy JIT engine 10 months ago then it probably still isn't.
-Andy
-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Rahul Garg
Sent: Tuesday, July 31, 2012 1:13 PM
To: llvmdev at cs.uiuc.edu
Subject: Re:
2008 Oct 07
1
FW: Reading Data
Rahul Agarwal
Analyst
Equities Quantitative Research
UBS_ISC, Hyderabad
On Net: 19 533 6363
hi let me explain you the problem
we have a database which is in this format
Stocks 30-Jan-08 28-Feb-08 31-Mar-08 30-Apr-08
a 1.00 3.00 7.00 3.00
b 2.00 4.00 4.00 7.00
c 3.00 8.00 655.00 3.00
d 4.00 23.00 4.00 5.00
e 5.00 78.00 6.00 5.00
and we have a query
2012 Jul 31
0
[LLVMdev] ARM JIT support status?
The only reference that I found so far here:
http://llvm.org/devmtg/2011-09-16/EuroLLVM2011-LLVMplusARM.pdf
The presenter states that the ARM JIT support is broken.
But this is about 10 months old.
Is the ARM JIT support still broken? Am I not looking at the right
places in the documentation?
Help will be appreciated.
thanks,
Rahul
On Mon, Jul 30, 2012 at 4:53 AM, Rahul Garg <rahulgarg44 at
2006 Nov 17
2
Forming SQL Query at run-time
Hi.
I am trying to get data from mysql database using a couple of queries.
I do one query to find out the indexes. Then i need to use these
indexes in another query, but i keep getting errors.
Here is something:
numb <- dbSendQuery(con2, "select distinct(comparison) from table1")
count <- fetch(numb, -1)
my.matrix <- as.matrix(count)
rs <- dbSendQuery(con2, "select
2008 Sep 24
1
[Bridge] bridge is not forwarding the packet
Hi Rahul,
If you're certain that your problem isn't as Stephen suggested, you
might want to have a look at this:
---
(From http://ebtables.sourceforge.net/brnf-faq.html
<http://ebtables.sourceforge.net/brnf-faq.html> )
How do I let vlan-tagged traffic go through a vlan bridge port and the
other traffic through a non-vlan bridge port?
Suppose eth0 and eth0.15 are ports of br0.
2017 Mar 10
1
virtual all mails folder in dovecot
I have Centos 7 mail server installed with dovecot and postfix with
MariaDB. I am trying to add a virtual All Mails folder for every user so
that they can have all mails such as inbox, sent in a single folder,
something like gmail. Please help me for this.
*Regards,*
*Rahul*
-------------- next part --------------
[rahul at surrey ~]$ dovecot --version
2.2.10
[rahul at surrey ~]$ dovecot -n
#
2017 Jul 19
3
Integration of Google Speech API V2
Hi Marcelo,
Thanks for replying, I do not know what this branch is.
Could you please let me know.
Also, I enabled google cloud speech API only from the console. Do I need
more API enabled?
On Wed, Jul 19, 2017 at 3:41 PM, Marcelo Terres <mhterres at gmail.com> wrote:
> Did you already tried the cloud_api branch?
>
> Regards,
>
> Marcelo H. Terres <mhterres at
2003 Nov 09
4
[LLVMdev] LLVM namespac'ification
Coming back to the issues that I had integrating LLVM with
MSSP, will the code in include/Support also be put in the
llvm namespace? That will solve many problems and help prevent
others.
Rahul
---- Original message ----
>Date: Sun, 9 Nov 2003 10:13:03 -0600 (CST)
>From: Chris Lattner <sabre at nondot.org>
>Subject: [LLVMdev] LLVM namespac'ification
>To: LLVMdev List
2003 Aug 13
1
[LLVMdev] Running a pass
Hi,
I want to run the Mem2Reg pass on a function without using the the LLVM opt utility. I wrote some code, which I am not sure is correct:
TS_ASSERT(!verifyFunction(*function));
// find the dominance frontier of the CFG
DominanceFrontier DF;
DF.runOnFunction(*function);
// try to promote stack allocated variables
PromoteMemToReg(function->getRegAllocas(), DF, *tgt_data);
2005 May 14
2
New queing discipline
I want to implement a new queuing discipline for the tool tc. The new
queuing discipline would support the application of multiple threads
on the same queue with different kinds of traffic. Each kind of packet
will have its own drop probability but while calculating the average
queue length, the no. of packets in the queue will be equal to the
sum of the individual no. of packets(of the different
2003 Sep 25
3
configuring TE410P for four E1 PRI lines
hi,
I'm trying to configure my newly acquired TE410P card to work as 4
E1 spans. This is
supposed to be a drop-in replacement to the earlier E100P card. However,
on loading the
zaptel module it gets configured as T1 spans basically doing a 'cat' on
/proc/zaptel/1 thru 4,
it shows 24 channels per span. After this ztcfg fails saying
'ZT_CHANCONFIG failed for channel 97'.
2012 Jul 30
2
[LLVMdev] ARM JIT support status?
Hi.
I am a little unclear about the ARM JIT support status. Is it working
as of LLVM 3.1? If not, is it on the roadmap for LLVM 3.2?
I am not currently interested in NEON support so if thats
unimplemented, thats fine.
thanks,
Rahul