similar to: [LLVMdev] Debugging/Fixing 'Interval not live at use' errors

On Oct 23, 2012, at 2:10 AM, Stephen McGruer <stephen.mcgruer at gmail.com> wrote: > I have a target backend which is currently causing live interval analysis to throw 'Interval not live at use' errors for many of my benchmarks. I imagine that this is caused by missing information for my target (probably in the instructioninfo tablegen?), but I am having difficulties in both

Thanks for the suggestion. I ran verify-machineinstrs and found that I've definitely been doing something wrong, for quite a while at least (I assume that live interval analysis and the particular benchmark just happened to expose it). Results are at http://pastebin.com/5zeUDVXK. I'm not entirely sure what is wrong here - I assume it has something to do with my 'special'

Hi Stephen, > I'm not entirely sure what is wrong here - I assume it has something to do > with my 'special' instruction LDri_ab. This instruction is a load with an > 'address writeback' - ld.ab r0, [r1, 5] is equivalent to ld r0, [r1]; add > r1, r1, 5. As it was very difficult to match such behaviour automatically, I > actually only generate them manually for

Here basically my problem is vector width since i have used v64i32 in my backend. now if vector width=64. i want the Reg_B class registers to be assigned and if vector width=2048 i want Reg_A registers to be assigned to instruction. Should i incorporate the solution in lowering stage? some thing like; addRegisterClass(MVT::v2048i32, &X86::Reg_B);

hello, i have a situation where i have to assign the registers to instructions based on the loop iterations. for eg.. the registers are: R_0_V_0, R_0_V_1, R_0_V_2, R_0_V_3, R_1_V_0, R_1_V_1, R_1_V_2, R_1_V_3, R_2_V_0, R_2_V_1, R_2_V_2, R_2_V_3. These registers defined in object Reg_A These are total 12 registers. will use them contiguously, here i define it in above mentioned order i.e

Is LiveVariables updated correctly when TII->RemoveBranch and TII->InsertBranch are called in the following piece of code? - MachineBasicBlock::updateTerminator() line 307 of MachineBasicBlock.cpp: if (FBB) { // The block has a non-fallthrough conditional branch. If one of its // successors is its layout successor, rewrite it to a fallthrough // conditional branch.

Hi, I am trying to do a backend to a very simple microcontroller. I have some questions. 1) I have instruction which do "r1 <- r1 op r2", from what I have ssen I must declare them like: let isTwoAddress = 1 in def ADD : FopRR< 0b01010, (outs CPURegs:$sX), (ins CPURegs:$isX, CPURegs:$sY), "ADD $sX, $sY"), [(set

On Apr 27, 2008, at 7:37 AM, Cédric Venet wrote: > Hi, > > I am trying to do a backend to a very simple microcontroller. I have > some > questions. Ok. > 1) I have instruction which do "r1 <- r1 op r2", from what I have > ssen I > must declare them like: > > let isTwoAddress = 1 in > def ADD : FopRR< 0b01010, > (outs

Hello, Thank you for your answer. If I want to use then I have error: ‘NodeTy* llvm::ilist_half_node<NodeTy>::getPrev() [with NodeTy = llvm::Instruction]’ is protected error: ‘llvm::ilist_half_node<llvm::Instruction>’ is not an accessible base of ‘llvm::Instruction’ Do you know any other method to access the previous instruction of a terminator instruction? PS: back() is not an

Hi all,I'm working on my own backend for a custom CPU. I have defined paired registers for 64bit operations, however to set a 64bit paired register with 64bit immediate I have to set each register in that pair separately with the higher and the lower 32bits of the immediate. Could anyone give me an advice how to describe it in *InstructionInfo.td or point me to something similar in the LLVM

Dear all, The architecture I am working with supports moving values directly from one register to another, or moving an immediate straight to a register, and I cannot figure out how to do this in LLVM. I originally tried matching something like [(set RegisterClass:$dest, RegisterClass:$src)] in my TargetInstrInfo.td: def MOVrr : MyInstrClass<(outs CPURegs:$dest), (ins CPURegs:$src),

I'm having trouble getting my backend to properly treat the situation where a char* is converted into a struct, i.e. something like: char* pointer_representation = ...; MyStruct* my_struct = (MyStruct*) pointer_representation; my_struct->an_int_field = 5; When this occurs, LLVM seems to fold the struct and char* into one assembly 'object', which is perfectly fine. However, it also

Hello David, Thanks for your example. Is that means that DAG pattern is consist of LLVM IR instruction?? I met an example [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))] of MipsInstrInfo.td, but I can't find correspond LLVM IR instruction of "set" in "LLVM Language Reference Manual". Is that correspond to $dst = op $b, $c?? Would you mind to tell me whether there is

If you could point me towards the correct location in the standard I would appreciate that - I didn't realize it wasn't acceptable to turn pointer-data to structs. My example is reduced from the EEMBC benchmarks where I ran into the problem, so I may have reduced it too far by accident (but I'm fairly sure they do not use __attribute__ or similar). Adding a

getPrevNode<http://llvm.org/docs/doxygen/html/classllvm_1_1ilist__node.html#a77b897207ef0a1ae95c404695aed9a4b>() Get the previous node, or 0 for the list head. I don't see any method like hasPrevNode. It can be a weird problem because "current->getPrevNode()" is indicating to "current" itself (the problem appears for the BB with only one element)? On Thu, Dec

On Fri, Oct 12, 2012 at 10:43 AM, Stephen McGruer <stephen.mcgruer at gmail.com> wrote: > I'm having trouble getting my backend to properly treat the situation where > a char* is converted into a struct, i.e. something like: > > char* pointer_representation = ...; > MyStruct* my_struct = (MyStruct*) pointer_representation; > my_struct->an_int_field = 5; > >

I solved by checking if(BB->size()>1) Thank you all for the help ! Now debugging the next segfault. On Thu, Dec 20, 2012 at 12:59 PM, Alexandru Ionut Diaconescu < alexandruionutdiaconescu at gmail.com> wrote: > getPrevNode<http://llvm.org/docs/doxygen/html/classllvm_1_1ilist__node.html#a77b897207ef0a1ae95c404695aed9a4b>() > Get the previous node, or 0 for the list

Do you want to replace lui $2, %hi(g1) addiu $2, $2, %lo(g1) with this? la $2, g1 If that is the case, you can add this pattern. def op_la : Operand<i32>; def LA : FI<0x09, (outs CPURegs:$dst), (ins op_la:$addr0, op_la:$addr1), "la $dst, $addr0", [(set CPURegs:$dst, (add (MipsHi tglobaladdr:$addr0), (MipsLo tglobaladdr:$addr1)))], IIAlu>;

On Mar 6, 2012, at 5:05 PM, Akira Hatanaka <ahatanak at gmail.com> wrote: > I am having trouble trying to enable post RA scheduler for the Mips backend. > > This is the bit code of the function I am compiling: > > (gdb) p MF.Fn->dump() > > define void @PointToHPoint(%struct.HPointStruct* noalias sret > %agg.result, %struct.ObjPointStruct* byval %P) nounwind {

I am having trouble trying to enable post RA scheduler for the Mips backend. This is the bit code of the function I am compiling: (gdb) p MF.Fn->dump() define void @PointToHPoint(%struct.HPointStruct* noalias sret %agg.result, %struct.ObjPointStruct* byval %P) nounwind { entry: %res = alloca %struct.HPointStruct, align 8 %x2 = bitcast %struct.ObjPointStruct* %P to double* %0 = load