similar to: [LLVMdev] % in tablegen

I think we want to apply the following patch to make the NumberValueRangeProcessor documentation (a) make sense, and (b) accurate: ---------------------------------------------------------------------- --- include/xapian/queryparser.h (revision 9993) +++ include/xapian/queryparser.h (working copy) @@ -213,7 +213,7 @@ * * For example, if str_ is "$" and prefix_

Hello! I am having a problem understanding what the weights option in the locfit command of the locfit package is doing. I have written a sample program which illustrates the issue (below). The example involves using bootstrap however, that is not my main goal but it illustrates where my problem lies. As you know, to compute a bootstrap estimate of a particular quantity using a sample size of

Hi, After seeing in "pbx/ael/ael-test/ael-test5/extensions.ael" some interesting use case of RealTime to store extension data (forwardto, dnd, ...) i started to play with it. To my surprise the two applications RealTime() / RealtimeUpdate() have been deprecated in favor of the REALTIME() function. While it's not a big deal for the write part since it's only a matter a shifting

In our architecture loads from certain memory locations take a long time to complete (on the order of 150 clock cycles). Since we don't have a way to tell at compile time if the address being loaded from lies in slow or fast memory, I've gone ahead and made all of the load numbers high, such as: InstrItinData< II_LOAD1, [InstrStage<150, [AGU]>]>, However, I see that

I have been reading the “RFC/bikeshedding: Separation of instruction and pattern definitions in LLVM backends” topic with considerable interest. This is an approach I have been considering for taming our own large instruction set, and it looks like it structures our descriptions better than the conventional approach we have used so far. However, I have another form of TableGen taming that I

I overrode getInstrLatency and did some printing to see what is available there. It looks like the registers are still virtual at that point when getInstrLatency is called - is that correct? (we needed to make some decisions based on actual registers that have been assigned since some registers are reserved as address space pointers and we could vary the latency based on which address space

Hi Eli, Thanks for your response. Actually, I look a lot at the ARM and THUMB1 backend implementations, and this certainly help. My architecture also have specific instructions for SP-relative accesses in a similar way than the Thumb1. During frame lowering, specific machine instructions are emitted so there’s no issue there. Also during ISelDagToDag I am able to select the right instructions.

Hi Craig, Thanks for the information. Can you point to the source that specifies tGPR to be R0 - R7? I tried to search in ARMInstrThumb.td but couldn’t find it. Thanks, - Jie On Apr 14, 2019, at 15:28, Craig Topper <craig.topper at gmail.com<mailto:craig.topper at gmail.com>> wrote: I believe there is probably a separate instruction in LLVM for thumb2 add. Probably starting with t2

Hi Dr. Viechtbauer, I'm doing meta-analysis using your package 'metafor'. I used the 'IRFT' to transform the incident rate. But when I tried to back-transform the summary estimates from function rma, I don't know what's the appropriate ti to feed in function transf.iirft. I searched and found your post about using harmonic mean for ni to back-transform the double

See previous version: https://www.redhat.com/archives/libguestfs/2016-April/msg00021.html The formatting in this second version isn't too bad. Still a few corner cases to sort out. Rich.

In MyTargetRegisterInfo.td file, I defined separated register classes for general purpose registers and for the SP register: def GR16 : RegisterClass<"CPU74", [i16], 16, (add R0, R1, R2, R3, R4, R5, R6, R7)>; def SSP : RegisterClass<"CPU74", [i16], 16, (add SP)>; The SP can not be used in general purpose arithmetic instructions, therefore I defined the following

Sorry for not being specific enough. ARMv7-M includes Thumb and Thumb2. It has 12 regular registers (R0 - R12), and R8 - R12 are used. I can generate mov instruction that from/ R8-R12 to/from R0-R6. From this ARM page http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0068b/ch03s03s01.html R9 - R12 have their conventional usage, but I don’t if this is the reason we cannot use them

Hi All, I have millions of regression lines to fit. So I am looking for the most efficient approach in R. Details: I have a large desing matrix X. The dimension is n by p. Each time when fitting the model, select rows from this matrix X and form a new design matrix, called X_current. There is another binary matrix M, with dim m by n, and each row is a 1*n vector. It helps to determin X_current.

I happen to be using LLVM for just this reason. I process large volumes of data records with schemas that are only known at runtime and/or can change dynamically as various transforms are applied to such records at various stages. To this end, I auto-generate C99 syntax at run time, parse it using clang, do some AST transformations, compile using LLVM JIT, and then execute within the same (C++)

Using C++ code, I would like to generate code at run-time (the same way .NET code can use dynamic methods or compiled expressions) in order to obtain very high performance code (to read binary data records whose formats are only known at run-time.) I need to target x86 (Win32) and ARM (WinCE). Can LLVM be used for this purpose, or would something else work better? Are there any open-source

Vlad wrote: > I happen to be using LLVM for just this reason. I process large volumes > of data records with schemas that are only known at runtime and/or can > change dynamically as various transforms are applied to such records at > various stages. > > To this end, I auto-generate C99 syntax at run time, parse it using > clang, do some AST transformations, compile using LLVM

Dear all, I have searched the forums for an answer - and there is plenty of questions along the same line - but none of the paproaches shown worked to my problem: I have a data frame that I get from a csv: summarystats<-as.data.frame(read.csv(file=f_summary)); where I have the columns Dataset, Class, Type, Category,.. Problem1: I want to find a subset of this frame, based on values in

* Kill the A8+A8 hack. Recent enough X servers (>=1.7) fall back to ARGB glyphs for drivers not supporting A8 render targets. * Kill all the global state. It doesn't matter a lot yet but it might if we get multicard working at some point. * Other random clean-ups with no functional changes. Some numbers from x11perf -aa10text -aa24text -comppixwin10 -comppixwin500: * Before, with A

Hello, using asterisk 1.8.11.1 using realtime queues When trying to remove a queue member, I get the following : -- Executing [122 at from-TESTCORP:2] RemoveQueueMember("SIP/testcorp5-0000000c", "testcorpq1,SIP/testcorp7") in new stack WARNING[18788]: app_queue.c:5653 rqm_exec: Unable to remove interface from queue 'testcorpq1': 'SIP/testcorp7' is not a

I edit two files named test.h,test.cpp as follow: ///////////////test.h////////////////////////////////////////////////////////////////class TestClass { private: int fTotal; public: TestClass(); ~TestClass(); };///////////test.cpp/////////////////////////////////////////////////////////////////////////////#include "test.h" TestClass::TestClass() { fTotal = 2; }