similar to: [LLVMdev] tablegen multiple inheritance question

Displaying 20 results from an estimated 10000 matches similar to: "[LLVMdev] tablegen multiple inheritance question"

2012 Jul 03
0
[LLVMdev] tablegen multiple inheritance question
Seems to just be a byproduct of TGParser::AddSubClass() begin called twice. This means that TGParser::AddValue() is being called once for the "i" of each class, and the "last one wins". Not sure if it is intended, but this behavior seems to more-or-less "make sense". --Sean Silva On Mon, Jul 2, 2012 at 4:55 PM, reed kotler <rkotler at mips.com> wrote: >
2012 Jul 03
3
[LLVMdev] bug in tablegen?
Not sure what you mean. I.OutOperandList == (outs CPU16Regs:$rx) I.InOperandList == (ins CPU16Regs:$ry, CPU16Regs:$rz) On 07/02/2012 09:26 PM, Sean Silva wrote: > I think you're missing the template args for `FRRR16_ins` in the first > argument. The switch in TGParser::ParseType() doesn't cover the case > of types with template args though... which makes me wonder what is
2012 Jul 04
0
[LLVMdev] bug in tablegen?
class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, InstrItinClass itin> : // ... This class has template args. You don't specify them in the first template arg of class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ... --Sean Silva On Tue, Jul 3, 2012 at 2:29 PM, reed kotler <rkotler at mips.com> wrote: > Not sure what you mean.
2012 Jul 05
2
[LLVMdev] bug in tablegen?
I think that what I did originally should have worked and the bug was correct as I reported it. Here is an alternate implementation which has the same problem. class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>: FRRR16<!cast<FRRR16_ins>(I).f, !cast<FRRR16_ins>(I).OutOperandList, !cast<FRRR16_ins>(I).InOperandList,
2012 Jul 05
0
[LLVMdev] bug in tablegen?
This variant works: class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>: FRRR16<!cast<FRRR16_ins>(I).f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz), // !cast<FRRR16_ins>(I).OutOperandList, // !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString, [(set CPU16Regs:$rx,
2012 Jul 03
2
[LLVMdev] bug in tablegen?
I've filed the following bug. Maybe I'm doing something stupid here or maybe someone knows of a workaround. The following fragment from mips16 (not yet checked into main source). The problem is that I should be able to pass parameters: I.OutOperandList, I.InOperandList But instead, I must back substitute what I know the values of these are. (outs CPU16Regs:$rx), (ins CPU16Regs:$ry,
2012 Jul 03
0
[LLVMdev] bug in tablegen?
I think you're missing the template args for `FRRR16_ins` in the first argument. The switch in TGParser::ParseType() doesn't cover the case of types with template args though... which makes me wonder what is going on inside of TableGen to make `I.f` and `I.AsmString` valid... --Sean Silva On Mon, Jul 2, 2012 at 8:07 PM, reed kotler <rkotler at mips.com> wrote: > I've filed
2014 Apr 24
3
[LLVMdev] tablegen for fast isel
What is the purpose of tablegen created files for fast-isel? If I make the following change to Makefile in lib/Target/Mips BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \ MipsGenAsmWriter.inc MipsGenCodeEmitter.inc \ MipsGenDAGISel.inc MipsGenCallingConv.inc \ - MipsGenSubtargetInfo.inc MipsGenMCCodeEmitter.inc \ +
2012 Jun 05
4
[LLVMdev] technical debt
On 06/04/2012 05:17 PM, Daniel Berlin wrote: > Can we get back to the substantive discussion about your ideas for > lessening the technical debt? The lessening requires enlisting people that are willing to do this as opposed to doing fun science like cool optimization. I,for example, find the documentaiton, cleanup and refactoring to be interesting so I don't feel cheated to work on
2012 Jun 05
0
[LLVMdev] technical debt
FWIW, I'm putting together (hopefully to be done by the end of this weekend) a substantial refactoring of the TableGen backend API along with shiny new documentation (reStructuredText with sphinx) of all of TableGen, including documentation about how to write backends and---depending on how adventurous I get---a more detailed coverage of the syntax. Also, Reed, in your TableGen talk, IIRC,
2012 Jun 05
2
[LLVMdev] technical debt
Hi Sean, Glad to hear there is clean up of tablegen going on. Just for the record, I don't know what you are referring to regarding some comment of mine at my talk about 10K LOC. I don't know how big tablegen is itself nor how much code has been written in it so I would not have ventured such a guess. The idea of totally replacing the tablegen language came up at the talk during the
2012 Mar 24
2
[LLVMdev] tablegen question
According to the TableGen manual: "Each def record has a special entry called "NAME." This is the name of the def ("ADD32rr" above). In the general case def names can be formed from various kinds of string processing expressions and NAME resolves to the final value obtained after resolving all of those expressions. The user may refer to NAME anywhere she desires to
2012 Mar 26
1
[LLVMdev] tablegen question
On 03/25/2012 07:52 PM, greened at obbligato.org wrote: > Reed Kotler<rkotler at mips.com> writes: > >> I agree that for multiclass it works more how you would expect it to. >> >> So, I don't think that NAME should be ? as in the example I gave. > I think you are right. I never tested it with regular classes because I > hadn't come across a use case.
2012 Jun 05
0
[LLVMdev] technical debt
I definitely trust what you say now with time to think at your keyboard over what you said on the spot in a live presentation. The comment that I was referring to was: 36:44 of http://llvm.org/devmtg/2012-04-12/videos/Reed_Kotler-mobile.mov "there's not really more than a couple thousand lines of .td ... I mean there's not tons of this code so if we had to use a different one I
2012 Jun 05
3
[LLVMdev] technical debt
Well, differences of opinion is what makes horse races. Reed On 06/04/2012 04:57 PM, Daniel Berlin wrote: > On Mon, Jun 4, 2012 at 7:53 PM, reed kotler<rkotler at mips.com> wrote: >> On 06/04/2012 03:25 PM, Daniel Berlin wrote: >>> I'm pretty sure neither llvm nor clang have any technical debt at all. >>> >>> On Mon, Jun 4, 2012 at 5:18 PM, reed
2014 Jun 11
2
[LLVMdev] constraining two virtual registers to be the same physical register
On 06/10/2014 05:51 PM, Pete Cooper wrote: > Hi Reed > > You can do this on the instruction itself by telling it 2 operands > must be the same register. For example, from X86: > > let Constraints = "$src1 = $dst" in > defm INSERTPS : SS41I_insertf32<0x21, "insertps">; > > Thanks, Hi Pete, Sorry. I should have been more specific. I'm
2012 Jun 05
0
[LLVMdev] technical debt
Can we get back to the substantive discussion about your ideas for lessening the technical debt? On Mon, Jun 4, 2012 at 8:05 PM, reed kotler <rkotler at mips.com> wrote: > Well, differences of opinion is what makes horse races. > > Reed > > > On 06/04/2012 04:57 PM, Daniel Berlin wrote: >> >> On Mon, Jun 4, 2012 at 7:53 PM, reed kotler<rkotler at
2014 Feb 25
3
[LLVMdev] configure with clang vs gcc
On 02/25/2014 02:38 PM, Eric Christopher wrote: > On Tue, Feb 25, 2014 at 2:32 PM, reed kotler <rkotler at mips.com> wrote: >> On 02/25/2014 09:30 AM, Richard Sandiford wrote: >>> reed kotler <rkotler at mips.com> writes: >>>> On 02/24/2014 04:42 PM, Eric Christopher wrote: >>>>> On Mon, Feb 24, 2014 at 4:40 PM, reed kotler <rkotler at
2012 Mar 26
0
[LLVMdev] tablegen question
Reed Kotler <rkotler at mips.com> writes: > I agree that for multiclass it works more how you would expect it to. > > So, I don't think that NAME should be ? as in the example I gave. I think you are right. I never tested it with regular classes because I hadn't come across a use case. But it should work. I'll see if I can fix it.
2012 Jun 04
2
[LLVMdev] technical debt
On 06/04/2012 03:25 PM, Daniel Berlin wrote: > I'm pretty sure neither llvm nor clang have any technical debt at all. > > On Mon, Jun 4, 2012 at 5:18 PM, reed kotler<rkotler at mips.com> wrote: >> something to think about as llvm and clang grows. >> >> http://en.wikipedia.org/wiki/Technical_debt >> _______________________________________________ >>