similar to: [LLVMdev] Question about CriticalAntiDepBreaker.cpp

My team interested in doing some post-RA optimizations on X86 instructions, which would require identifying memory reference instructions. In the X86 back end instructions, memory addresses consist of a set of five operands. The offset to the start of the five operands depends on the format of the instruction. For instance, the instructions ADC32rm, ADD32rm, AND32rm, ANDN32rm, CMOVA32rm,

Hello Andy, Thank you for your offer to work together on implementing the your new scheduler on X86. I can start working on this right away. In case you were unaware, the new Silvermont micro-architecture is only out of order on the integer side. The SSE instructions are still in order, so the current postRA scheduler is very beneficial for code with lots of SSE instructions, such as the ISPC

When trying to run test/CodeGen/X86/liveness-local-regalloc.ll with the command line options "-optimize-regalloc=0 -verify-machineinstrs -mcpu-atom", the test fails right after the Post-RA pseudo instruction pass with the messages *** Bad machine code: Using an undefined physical register *** - function: autogen_SD24657 - basic block: BB 0x2662d60 (BB#0) - instruction:

Using the following example program #include <math.h> double f(double d){ return sqrt(d); } and compiling it with "clang -O3 ...", I was trying to determine what it would take to get the X86 code generator to replace the call to sqrt with a sqrtsd instruction inline. It turns out that it could do exactly that, were it not for the fact that in the function

When you compile the attached file using llc -march=x86 -mcpu=atom sched-bug.ll -o - The Post-RA scheduler changes the sequence movl %ecx, (%esp) bsfl (%esp),%eax # this came from inline assembly code to read bsfl (%esp),%eax # this came from inline assembly code movl %ecx, (%esp) This is an incorrect schedule, because it seems the scheduler is not aware that the memory

On 21.05.2013, at 23:03, "Gurd, Preston" <preston.gurd at intel.com> wrote: > Thanks for the fix! > > However, there still seems to be a problem in that if you pass –ffast-math to clang, then clang changes “sqrt” to be “__sqrt_finite”. LLVM cannot then change the function call into an x86 sqrt instruction, even with –fno-math-errno set. > > Can you suggest

On May 17, 2013, at 3:33 PM, "Gurd, Preston" <preston.gurd at intel.com> wrote: > Using the following example program > > #include <math.h> > > double f(double d){ > return sqrt(d); > } > > and compiling it with “clang –O3 …”, I was trying to determine what it would take to get the X86 code generator to replace the call to sqrt with a

Since Clang does not seem to allow type casts, such as uchar4 to float4, between vector types, it seems it is necessary to write them as element by element conversions, such as typedef float float4 __attribute__((ext_vector_type(4))); typedef unsigned char uchar4 __attribute__((ext_vector_type(4))); float4 to_float4(uchar4 in) { float4 out = {in.x, in.y, in.z, in.w}; return out; } Running

-- Preston Gurd <preston.gurd at intel.com> Intel Waterloo SSG/DPD/ECDL/DMP -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120409/b78a88d6/attachment.html>

On Nov 20, 2008, at 8:31 AM, Preston Gurd wrote: > Might you instead consider just adding a -disable-mmx option? I agree, this is a better approach. This distinguishes between capabilities of the chip and the desire to codegen specific vectors one way or another. -Chris > > Preston > > On Thu, 2008-20-11 at 02:57 -0500, Mon Ping Wang wrote: >> Hi, >> >>

Hi Anton, I ran llc with -verify-coalescing. There were no error messages. Then I added code in MipsPassConfig::addPreEmitPass() to prevent machine verifier from running post delay -slot-filler, and ran llc again. Again, there were no error messages. This is the list of passes run after post-RA scheduling. machine verifier is run twice after post RA scheduler (and CriticalAntiDepBreaker) is run.

Sorry, I meant to say, I added code to prevent llc from running machine verifier after delay slots are filled. MipsInstrInfo::AnalyzeBranch generates incorrect results after delay slots are filled. Also, it seems that code in MachineVerifier.cpp wasn't written with architectures that have delay slots in mind. On Wed, Apr 25, 2012 at 11:59 AM, Akira Hatanaka <ahatanak at gmail.com>

Dear LLVMdev, I've noticed an unusual behavior of the LLVM x86 code generator (with default options) that results in nearly a 4x slow-down in floating-point throughput for my microbenchmark. I've written a compute-intensive microbenchmark to approach theoretical peak throughput of the target processor by issuing a large number of independent floating-point multiplies. The distance

I am running into a problem when I turn on post-RA scheduler with mode "ANTIDEP_CRITICAL" for mips. I'd appreciate if someone could explain what is going wrong here. This is the basic block before post RA scheduling (at PostRASchedulerList.cpp:322): *(gdb) #3 0x0000000000ed3d26 in runOnMachineFunction (this=0x20aa470, Fn=...) at lib/CodeGen/PostRASchedulerList.cpp:322 322

Thanks for the fix! However, there still seems to be a problem in that if you pass –ffast-math to clang, then clang changes “sqrt” to be “__sqrt_finite”. LLVM cannot then change the function call into an x86 sqrt instruction, even with –fno-math-errno set. Can you suggest where I might look in the clang code to find the place where “sqrt” is converted to “__sqrt_finite” and/or the best way to

Hi Akira, > When I add -verify-machineinstrs, it complains that there are instructions > after terminator instructions. Yes, -verify-machineinstrs and -verify-coalescing are your friends here :) -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University

Hi Anton, Thanks for the suggestions. I compiled the .ll file with llc with command line options -verify-dom-info, -verify-regalloc and -verify-loop-info. I didn't see any diagnostic messages. When I add -verify-machineinstrs, it complains that there are instructions after terminator instructions. It seems that these error messages are printed because the verifier does not understand that

Hi, While investigating a performance issue with an internal codebase I came across what looks to be poor register allocation. I have constructed a small(ish) reproducible which demonstrates the issue (see test.ll attached). I have spent some time going through the register allocator to understand what is happening. I have also experimented with some small changes to try and improve the

Does fast-math imply no-math-errno ? Thanks, Nadav On May 17, 2013, at 15:36, Chris Lattner <clattner at apple.com> wrote: > > On May 17, 2013, at 3:33 PM, "Gurd, Preston" <preston.gurd at intel.com> wrote: > >> Using the following example program >> >> #include <math.h> >> >> double f(double d){ >> return sqrt(d);

Hi Akira, > I am running into a problem when I turn on post-RA scheduler with mode > "ANTIDEP_CRITICAL" for mips. > I'd appreciate if someone could explain what is going wrong here. All these passes are pretty sensitive to correct register liveness information. As a first step I'd check whether machine verifier reports no errors here. -- With best regards, Anton