Displaying 20 results from an estimated 10000 matches similar to: "[LLVMdev] tablegen nomenclature"
2012 Jul 05
2
[LLVMdev] bug in tablegen?
I think that what I did originally should have worked and the bug was
correct as I reported it.
Here is an alternate implementation which has the same problem.
class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>:
FRRR16<!cast<FRRR16_ins>(I).f,
!cast<FRRR16_ins>(I).OutOperandList,
!cast<FRRR16_ins>(I).InOperandList,
2012 Jul 05
0
[LLVMdev] bug in tablegen?
This variant works:
class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>:
FRRR16<!cast<FRRR16_ins>(I).f,
(outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz),
// !cast<FRRR16_ins>(I).OutOperandList,
// !cast<FRRR16_ins>(I).InOperandList,
!cast<FRRR16_ins>(I).AsmString,
[(set CPU16Regs:$rx,
2014 Apr 24
3
[LLVMdev] tablegen for fast isel
What is the purpose of tablegen created files for fast-isel?
If I make the following change to Makefile in lib/Target/Mips
BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \
MipsGenAsmWriter.inc MipsGenCodeEmitter.inc \
MipsGenDAGISel.inc MipsGenCallingConv.inc \
- MipsGenSubtargetInfo.inc MipsGenMCCodeEmitter.inc \
+
2012 Jul 04
0
[LLVMdev] bug in tablegen?
class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern,
InstrItinClass itin> : // ...
This class has template args. You don't specify them in the first
template arg of
class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ...
--Sean Silva
On Tue, Jul 3, 2012 at 2:29 PM, reed kotler <rkotler at mips.com> wrote:
> Not sure what you mean.
2012 Jul 03
3
[LLVMdev] bug in tablegen?
Not sure what you mean.
I.OutOperandList == (outs CPU16Regs:$rx)
I.InOperandList == (ins CPU16Regs:$ry, CPU16Regs:$rz)
On 07/02/2012 09:26 PM, Sean Silva wrote:
> I think you're missing the template args for `FRRR16_ins` in the first
> argument. The switch in TGParser::ParseType() doesn't cover the case
> of types with template args though... which makes me wonder what is
2014 Feb 25
2
[LLVMdev] configure with clang vs gcc
I see what my problem is here....
I'll continue to move further.
Seems like Richards fix is still okay.
On 02/25/2014 02:42 PM, Eric Christopher wrote:
> On Tue, Feb 25, 2014 at 2:41 PM, reed kotler <rkotler at mips.com> wrote:
>> On 02/25/2014 02:38 PM, Eric Christopher wrote:
>>> On Tue, Feb 25, 2014 at 2:32 PM, reed kotler <rkotler at mips.com> wrote:
2014 Feb 25
3
[LLVMdev] configure with clang vs gcc
On 02/25/2014 02:38 PM, Eric Christopher wrote:
> On Tue, Feb 25, 2014 at 2:32 PM, reed kotler <rkotler at mips.com> wrote:
>> On 02/25/2014 09:30 AM, Richard Sandiford wrote:
>>> reed kotler <rkotler at mips.com> writes:
>>>> On 02/24/2014 04:42 PM, Eric Christopher wrote:
>>>>> On Mon, Feb 24, 2014 at 4:40 PM, reed kotler <rkotler at
2014 Feb 25
3
[LLVMdev] configure with clang vs gcc
On 02/24/2014 04:42 PM, Eric Christopher wrote:
> On Mon, Feb 24, 2014 at 4:40 PM, reed kotler <rkotler at mips.com> wrote:
>> I need to leave soon and will take a look in the morning.
>>
>> I did look at the autoconf input files configure.ac
>>
>> There is a disable-zlib but not a disable-valgrind, even though it seems
>> like there used to be.
2012 Mar 26
1
[LLVMdev] tablegen question
On 03/25/2012 07:52 PM, greened at obbligato.org wrote:
> Reed Kotler<rkotler at mips.com> writes:
>
>> I agree that for multiclass it works more how you would expect it to.
>>
>> So, I don't think that NAME should be ? as in the example I gave.
> I think you are right. I never tested it with regular classes because I
> hadn't come across a use case.
2014 Jun 11
2
[LLVMdev] constraining two virtual registers to be the same physical register
On 06/10/2014 05:51 PM, Pete Cooper wrote:
> Hi Reed
>
> You can do this on the instruction itself by telling it 2 operands
> must be the same register. For example, from X86:
>
> let Constraints = "$src1 = $dst" in
> defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
>
> Thanks,
Hi Pete,
Sorry.
I should have been more specific.
I'm
2014 Sep 30
2
[LLVMdev] ptrtoint
If you can't make an executable test from C or C++ code then how do you
know something works.
Just by examination of the .s?
On 09/30/2014 03:18 PM, Reed Kotler wrote:
> If I wanted to call this function that they generated by hand, from C or
> C+ code, how would that be done?
>
> if have seen cases where a real boolean gets generated but it was
> something fairly involved.
2012 Jun 28
2
[LLVMdev] recursing llvm
Okay. Cool.
So do you bootrstrap and verify as part of the usual testing?
Do the nightly scripts do this?
Reed
On 06/28/2012 11:08 AM, Eric Christopher wrote:
> On Jun 27, 2012, at 10:48 PM, Reed Kotler<rkotler at mips.com> wrote:
>
>> On 06/27/2012 05:00 PM, Eric Christopher wrote:
>>> On Jun 19, 2012, at 5:24 PM, reed kotler<rkotler at mips.com> wrote:
2013 Sep 18
2
[LLVMdev] forcing two instructions to be together
I used the A9 schedule as an example:
http://llvm.org/svn/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
The documentation could use more clarity, but this is how I was able to do it to always get two specific instructions to be scheduled together.
________________________________________
From: reed kotler [rkotler at mips.com]
Sent: Tuesday, September 17, 2013 8:54 PM
To: Micah Villmow
2012 Jun 05
3
[LLVMdev] technical debt
Well, differences of opinion is what makes horse races.
Reed
On 06/04/2012 04:57 PM, Daniel Berlin wrote:
> On Mon, Jun 4, 2012 at 7:53 PM, reed kotler<rkotler at mips.com> wrote:
>> On 06/04/2012 03:25 PM, Daniel Berlin wrote:
>>> I'm pretty sure neither llvm nor clang have any technical debt at all.
>>>
>>> On Mon, Jun 4, 2012 at 5:18 PM, reed
2012 Jun 05
0
[LLVMdev] technical debt
FWIW, I'm putting together (hopefully to be done by the end of this
weekend) a substantial refactoring of the TableGen backend API along with
shiny new documentation (reStructuredText with sphinx) of all of TableGen,
including documentation about how to write backends and---depending on how
adventurous I get---a more detailed coverage of the syntax.
Also, Reed, in your TableGen talk, IIRC,
2012 Jun 05
2
[LLVMdev] technical debt
Hi Sean,
Glad to hear there is clean up of tablegen going on.
Just for the record, I don't know what you are referring to regarding
some comment of mine
at my talk about 10K LOC.
I don't know how big tablegen is itself nor how much code has been
written in it so I would not have ventured such a guess.
The idea of totally replacing the tablegen language came up at the talk
during the
2014 Feb 25
2
[LLVMdev] configure with clang vs gcc
On 02/25/2014 09:30 AM, Richard Sandiford wrote:
> reed kotler <rkotler at mips.com> writes:
>> On 02/24/2014 04:42 PM, Eric Christopher wrote:
>>> On Mon, Feb 24, 2014 at 4:40 PM, reed kotler <rkotler at mips.com> wrote:
>>>> I need to leave soon and will take a look in the morning.
>>>>
>>>> I did look at the autoconf input files
2013 Sep 17
2
[LLVMdev] forcing two instructions to be together
Reed,
Couldn't you also use instruction scheduling classes and specify that the second instruction has a bypass from the first instruction? The scheduler should always schedule them together in that case.
Micah
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On
> Behalf Of reed kotler
> Sent: Tuesday, September 17, 2013
2012 Jun 05
0
[LLVMdev] technical debt
Can we get back to the substantive discussion about your ideas for
lessening the technical debt?
On Mon, Jun 4, 2012 at 8:05 PM, reed kotler <rkotler at mips.com> wrote:
> Well, differences of opinion is what makes horse races.
>
> Reed
>
>
> On 06/04/2012 04:57 PM, Daniel Berlin wrote:
>>
>> On Mon, Jun 4, 2012 at 7:53 PM, reed kotler<rkotler at
2015 Mar 19
4
[LLVMdev] Final added to parser<bool>
Well, you are an mclinker contributor and Google uses mclinker and now
it's broken as the result of your change.
I still don't see any justification to making a change in a public
interface that is used by other non LLVM projects
to fix some issue with clang warnings. People should be able to derive
from those classes. I can't understand
your reasoning as to why these classes must