similar to: [LLVMdev] Register mask operands

Hi Marcello, Thanks for your reply. I will try to pass down the mask! I have one more question. In my backend I return CSR_RegMask in getCallPreservedMask and return CSR_SaveList in getCalleeSavedRegs. Is that a correct setup? I dumped the regmask and found that callee saved regs are marked 1 and non-callee saved regs are 0. Thanks, Xiaochu On Wed, Aug 26, 2015 at 5:58 PM Marcello Maggioni

> On Jun 28, 2016, at 10:09 AM, Mehdi Amini via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > > Sent from my iPhone > > On Jun 28, 2016, at 12:53 PM, vivek pandya <vivekvpandya at gmail.com <mailto:vivekvpandya at gmail.com>> wrote: > >> >> >> On Tue, Jun 28, 2016 at 8:11 PM, Mehdi Amini <mehdi.amini at apple.com

Dear there, I was wondering how to preserve registers (caller saved) across calls. I implemented getCalleeSavedRegs and getCallPreservedMask. But the non-callee-saved registers are still not saved by caller. I want to spill these registers in use on stack right before the call. From my understanding, the register allocator in llvm will do the spill and restoring automatically? Is there anything I

Hi, I have attached WIP patch for adding foldMemoryOperand to Thumb1InstrInfo. For the following case: void f(int x, int y, int z) { void bar(int, int, int); bar(x, y, z); bar(x, z, y); bar(y, x, z); bar(y, y, x); } it calls foldMemoryOperand twice, and thus converts two calls from blx to bl. callMI->dump() shows the function name "bar" correctly, however in generated

Sent from my iPhone > On Jun 28, 2016, at 2:27 PM, Matthias Braun <matze at braunis.de> wrote: > > >> On Jun 28, 2016, at 10:09 AM, Mehdi Amini via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >> >> >> Sent from my iPhone >> >>> On Jun 28, 2016, at 12:53 PM, vivek pandya <vivekvpandya at gmail.com> wrote:

Hi, Compiling attached test-case, which is reduced version of of uECC_shared_secret from tinycrypt library [1], with --target=arm-linux-gnueabi -march=armv6-m -Oz -S results in reloading of register holding function's address before every call to blx: ldr r3, .LCPI0_0 blx r3 mov r0, r6 mov r1, r5 mov r2, r4 ldr r3,

Hi All, I'm trying to compile the attached code(gdb11531.c) with latest clang with -O0 on ARM. Clang seems to be reordering the instructions in case of constant nodes(for ARM) even when O0 is specified resulting in few wrong information when debugging through GDB. I had few queries,would be great if someone could clarify the same - In the given assembly code, the instructions where constant

On Jun 24, 2012, at 7:18 AM, Karel Gardas <karel.gardas at centrum.cz> wrote: > > Hello, > > first of all: one of the LLVM 3.0 new feature was a support for GHC specific calling convention on ARM platform. It looks like this support was merged just into 3.0 branch, specifically it appeared in 3.0 RC2. > Anyway, I hope this is just a mistake or omission that such support was

On Oct 19, 2010, at 6:37 PM, Roland Scheidegger wrote: > Thanks for giving it a look! > > On 19.10.2010 23:21, Jakob Stoklund Olesen wrote: >> On Oct 19, 2010, at 11:40 AM, Roland Scheidegger wrote: >> >>> So I saw that the code is doing lots of register >>> spilling/reloading. Now I understand that due to calling >>> conventions, there's not

Hello, first of all: one of the LLVM 3.0 new feature was a support for GHC specific calling convention on ARM platform. It looks like this support was merged just into 3.0 branch, specifically it appeared in 3.0 RC2. Anyway, I hope this is just a mistake or omission that such support was merged only into 3.0 and not also into HEAD. I've just found it by testing LLVM 3.1 with GHC 7.4.2 and

I am running into a problem when I turn on post-RA scheduler with mode "ANTIDEP_CRITICAL" for mips. I'd appreciate if someone could explain what is going wrong here. This is the basic block before post RA scheduling (at PostRASchedulerList.cpp:322): *(gdb) #3 0x0000000000ed3d26 in runOnMachineFunction (this=0x20aa470, Fn=...) at lib/CodeGen/PostRASchedulerList.cpp:322 322

Sent from my iPhone > On May 27, 2016, at 6:55 PM, vivek pandya <vivekvpandya at gmail.com> wrote: > > > >> On Sat, May 28, 2016 at 12:23 AM, vivek pandya <vivekvpandya at gmail.com> wrote: >> >> >>> On Sat, May 28, 2016 at 12:21 AM, Mehdi Amini <mehdi.amini at apple.com> wrote: >>> >>> > On May 27, 2016, at 11:49

Sent from my iPhone > On May 27, 2016, at 7:02 PM, vivek pandya <vivekvpandya at gmail.com> wrote: > > > >> On Sat, May 28, 2016 at 7:29 AM, Matthias Braun <matze at braunis.de> wrote: >> >>> On May 27, 2016, at 6:55 PM, vivek pandya via llvm-dev <llvm-dev at lists.llvm.org> wrote: >>> >>> >>> >>> On

> On May 27, 2016, at 11:49 AM, vivek pandya <vivekvpandya at gmail.com> wrote: > > Hello Mentors, > > I have completed writing simple register mask calculator pass, an immutable pass that stores RegMasks and provides API to query them, and a target specific pass for X86 target which currently iterates through all MI in given MF and if a call instruction is found then it

Hello Mentors, I have completed writing simple register mask calculator pass, an immutable pass that stores RegMasks and provides API to query them, and a target specific pass for X86 target which currently iterates through all MI in given MF and if a call instruction is found then it quires for RegMask to Immutable pass and prints which registers are clobbered and preserved as per actual

On Sat, May 28, 2016 at 12:23 AM, vivek pandya <vivekvpandya at gmail.com> wrote: > > > On Sat, May 28, 2016 at 12:21 AM, Mehdi Amini <mehdi.amini at apple.com> > wrote: > >> >> > On May 27, 2016, at 11:49 AM, vivek pandya <vivekvpandya at gmail.com> >> wrote: >> > >> > Hello Mentors, >> > >> > I have

Hi Mehdi, I wasn’t familiar with IPRA before, thank you for bringing it up. After studying it, I have to say that IPRA is a wonderful idea and is well implemented. I tried to reuse the mechanism for the last couple of days. I implemented a solution using IPRA mechanism and encountered few issues: 1. IPRA uses immutable analysis pass called “PhysicalRegisterUsageInfo”. The usage of such

Here in an example that explains the difference. // Only declaration – No implementation // Assume that the value is returned in EAX and the arguments are passed in EAX, ECX, EDX, ESI, EDI. int __regcall callee (int a, int b, int c, int d, int e); // implemented in a different module void caller() { … x = callee(1,2,3,4,5); … } What will be RegMask using IPRA register usage collector? Callee

Hi Mehdi, I think that the subject of the RFC is misleading. The true problem that we are trying to solve is to remove returned/passed arguments from the regmask (According to the calling convention). IPRA and CC updated RegMask can’t use the same mechanism because they contradict each other. I think that the following analog will help to explain why I think that a reuse is redundant: Let’s

After PrologEpilogCodeInserter I found that the instructions that restore callee saved registers S0,S1,LR are in the wrong location ,the instructions are: %S0<def> = LD %SP, 36; mem:LD4[FixedStack2] %S1<def> = LD %SP, 40; mem:LD4[FixedStack1] %LR<def> = LD %SP, 44; mem:LD4[FixedStack0] (LR is the Return address register) the whole code of print-machineinstrs are: # After