similar to: [LLVMdev] LinkModules triple/datatype mismatch warnings a bit strict?

Hello, I wanted to know about the reasons Apple dropped the support for "arm" target in its ld64. After searching in the sourcecode I found out that ld64 supports armv4 armv5 armv6 armv7 and its subtypes. The code shows that -force_cpusubtype_ALL for ARM targets is no more supported in "src/ld/options.cpp") and static const ARMSubType ARMSubTypes[] doesn't include

optimizations done for this CPU architecture. Whether it is in-line assembly or assembly optimization of function (Eg: celt_pitch_xcorr_arm.s), or using intrinsics, it is still some optimizations. So, I don't understand your perspective. I really thought about this for the most amount of time... could you please suggest an alternative here?.. Because I'm really out of ideas in this area

The use case is to create a module A, JIT from it, then extend the module with new code (create a new module B and use Linker::LinkModules() to merge into A, and be able to JIT the new symbols). This appears to work ok, except that static constructors are giving me a headache. Generally, I start like this: Create module A (e.g. via Clang, LLVM API etc.) EE->addModule(A);

I wrote a proof of concept regarding the cpu capabilities runtime detection and choice of optimized function. I follow design which had been discussed on IRC. Also, i notice a little drawback: we must propagate the arch index through functions which don't have codec state as argument. However, if it's look good, i will continue to implement it. Best regards, -- Aur?lien Zanelli

Hi, Paul Curtis wrote: > If you read the Arm Architecture document for ARMv5, it states for MUL: > > "Operand restriction: Specifying the same register for <Rd> and <Rm> was > previously described as producing UNPREDICTABLE results. There is no > restriction in ARMv6, and it is believed all relevant ARMv4 and ARMv5 > implementations do not require this

Hi, > I am using a cross compiler to compiler for the arm5 architecture. For this > architecture it is not allowed that a destination register is also used as source > register. > In 2007 a patch was discussed at the mailing list, however my compiler still is > producing this result. Does anyone know if this patch is actually applied? > > * I use the following arguments:

> My copy of the ARM ARM says: > > "Use of R15: Specifying R15 for register <Rd>, <Rm>, or <Rs> has > UNPREDICTABLE results." > > This is the same as above. However, it goes on to say: > > "Operand restriction: Specifying the same register for <Rd> and <Rm> was > previously described as producing UNPREDICTABLE results. There

On Mon, 18 Sep 2006, [UTF-8] Rafael Esp?ndola wrote: >> "The destination register shall not be the same as the operand >> register Rm. R15 shall not be used as an operand or as the >> destination register." > > The ARM ARM has this "Operand restriction" on MUL: > Specifying the same register for <Rd> and <Rm> has UNPEDICTABLE

Evan, > I'm the code owner of LLVM codegen and targets. I'm also the one of main developers on the original ARM target. That means, I would make the decisions on major development on ARM target if there are decisions to be made. > > But my role is very different from what people are looking for in this thread. To properly qualify a target like ARM which are supported on many

Hello, Nathan >   I may need to clarify, sparcv9-* is used for the SPARCV9 ABI (ie 64-bit ABI), rather than the SPARCV9 CPU per se. It serves the same purpose as x86_64-* and powerpc64-*, which is to say it's associated with -m64, not -mcpu=v9 (although unsurprisingly -m64 does require a V9 or later CPU). I may be wrong, but I think the only distinction in ARM is between arm and thumb

In the help command when i checked the processors supported by llvm 2.9 it showed arm926ej-s. which means thumb mode is supported right? this belongs to armv5. but the llvm documentation says thumb mode is supported only for armv6 and higher.. does it mean there is only a partial support for this processor? -------------- next part -------------- An HTML attachment was scrubbed... URL:

Good day, I have looked around for this information, but I have not been able to gain a clear understanding: what is the status of the LLVM ARM backend? That is, do the following work: 1. Generating Thumb code: I saw a video online where they describe an issue with using the ARM Thumb back-end 2. Generating code for ARM9 (ARMv5?) or ARM7 (ARMv4): again, the same presentation

On Sep 17, 2008, at 3:00 PM, Tyler Wilson wrote: > Good day, > > I have looked around for this information, but I have not been able > to gain a clear understanding: what is the status of the LLVM ARM > backend? That is, do the following work: > > 1. Generating Thumb code: I saw a video online where they > describe an issue with using the ARM Thumb back-end

Hi,     I am able to crosscompile llvm-gcc using --with-arch=armv6 but cannot using --with-arch=armv5. Can anyone please tell me what option i should use to crosscIompile for the architecture armv5te (xscale processor). I heard that by default arm 5 code generates, will that work on my target (armv5te)? I get the following when I use --with-arch=armv5 :    

Hi, I've been thinking about ways to get around this in the short term for some time, http://llvm.org/bugs/show_bug.cgi?id=1388 An end-user workaround is possibly to use at least one register > r7 for the MOV form of the instruction. In that case, what is listed in the bug as the CPY instruction (which is the ARMv6 version generated if both Rd and Rm are <= r7) will become a valid MOV

I'm running into a compile problem with commit 131656 of compiler-rt. I'm compiling llvm with: $ CXX='g++ -m32' CC='gcc -m32' CFLAGS=-m32 CXXFLAGS=-m32 LDFLAGS=-m32 ./configure --disable-bindings --{build,host,target}=i686-apple-darwin --enable-targets=x86,x86_64,cbe --enable-optimized $ make $ make install It will eventually error out with:

A new pixman release 0.34.0 is now available. This is a major release, following three development releases in the past six months. It contains all the changes detailed in the last three development releases in the 0.33 series. Please note that this release doesn't contain any changes since the previous development version (0.33.6) was released. For those who didn't follow the

I have a question regarding ARM support. It was mentioned in mails below that LLVM supports ARM v6 but a lot of ARM v6 instructions are actually missing from ARM ISA description files( e.g. Media Instructions). Is there any documentation mentioning the unsupported parts of v6 version Thanks --Kapil On Thu, Sep 18, 2008 at 2:14 PM, Evan Cheng <evan.cheng at apple.com> wrote: > > On

Can you give some examples of missing instructions? Evan On Oct 9, 2008, at 4:58 PM, kapil anand wrote: > I have a question regarding ARM support. It was mentioned in mails > below that LLVM supports ARM v6 but a lot of ARM v6 instructions are > actually missing from ARM ISA description files( e.g. Media > Instructions). Is there any documentation mentioning the unsupported

A new pixman release 0.33.2 is now available. This is a release candidate for a stable 0.34.0 release. This release comes after little more than 1 year since the previous release (0.32.6). Therefore, the git log is quite long and there are multiple changes, fixes and enhancements. The main changes are: - ARMv6 - Many fast paths implementations were added - PPC64/PPC64LE - Fix all outstanding