similar to: [LLVMdev] Problem generating <target>GenAsmMatcher.inc

I'm trying to generate MipsGenAsmMatcher.inc for MipsAsmParser.cpp. What added restrictions for the .td file contents are there for tblgen -gen-asm-matcher? For the Mips platform we create the following .inc files through tblgen. tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info) tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info) tablegen(LLVM MipsGenCodeEmitter.inc -gen-emitter)

Hi Jack, On Jan 25, 2012, at 6:45 PM, "Carter, Jack" <jcarter at mips.com> wrote: > I'm trying to generate MipsGenAsmMatcher.inc for MipsAsmParser.cpp. > > What added restrictions for the .td file contents are there for tblgen -gen-asm-matcher? > Lots, as you're finding, almost all of them completely undocumented. :( > For the Mips platform we create

This was reported by me (and most likely others). Here is the exchange about this. The reason the problem is visible in Delphi is that Borland (C++ and Delphi) initialize the FPU differently from other RTLs. Also, there is another problem that will be visible with Delphi --------------------------------------------------------- ------------- Yes, that's definitely a bug in the vbr code,

Hi! It seems that using a different compiler (I assume the development is done with MSC) uncovers various issues with the floating point. Here is the second one I'm seeing - DOMAIN error from sqrt(). In the open_loop_nbest_pitch(), this line: g = DIV32(corr[i-start], 10+SHR32(MULT16_16(spx_sqrt(e0),spx_sqrt(energy[i-start]) ),6)); The values are: e0 is 7.2 i is 142, start is 17

Hi, Ref the disucussion on IRC yesterday; here's a patch which makes a bit more data from the analysis of the preprocessor and the echo canceller available. For the preprocessor: - Size of power spectrum. - Power spectrum and noise estimate of the previous frame. These are given as squared values, so sqrt() to get values in the 0->32767 range. - Current amplification level

What is the purpose of tablegen created files for fast-isel? If I make the following change to Makefile in lib/Target/Mips BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \ MipsGenAsmWriter.inc MipsGenCodeEmitter.inc \ MipsGenDAGISel.inc MipsGenCallingConv.inc \ - MipsGenSubtargetInfo.inc MipsGenMCCodeEmitter.inc \ +

Hi all, My question is related to the register usage in instruction definition at TARGETInstrInfo.td file. I have defined new Target with it Registers and instructions. Now I need to generate an instruction like: mov MYREG1_NAME, MYREG2_NAME for the built-in function taking one constant integer argument, such as "__builtin_my_function_name(88)" I wondering whether it is possible

I'm getting this incompatible type assertion when I run tblgen on my .td files: llvm/include/llvm/Support/Casting.h:237: typename llvm::cast_retty<X, Y*>::ret_type llvm::cast(Y*) [with X = llvm::DefInit; Y = llvm::Init; typename llvm::cast_retty<X, Y*>::ret_type = llvm::DefInit*]: Assertion `isa<X>(Val) && "cast<Ty>() argument of incompatible

In our generated asm code we've got a constraint such that two registers in a ternary op have to be in different "banks", best illustrated with an example: add r1,r2,r1 # r1 <- r2 + r1 The problem here is that the first operand (the receiver of the value) is in the same "bank" as the 3rd operand (r1 again). This will cause an extra cycle to be burned. As it turns

I emailed Jean-Marc the arch.h about one week ago, not quite sure whether he actually received that email. Anyway, here I have an improved version of arch.h that I believe that it would be better, to use __int64 only if compiling on eMbedded Visual C++ compiler, so for any other compiler, keep it the same (use long long) ---------------------------------- Chan Kei Yuen (Kenji)

Here's an example piece of code to show you what I'm trying to do (on llvm 3.1): class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode, InstrItinClass itin, RegisterClass RC, bit isComm = 0>: FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), !strconcat("+$rd=$rs ",!strconcat(instr_asm, " $rt")),

Dear all. I have a problem with the following situation: I want to handle an intrinsic function in a specific way. The prototype of my function is: "/int my_intrinsic_name()/" So I want to generate a move instruction which should use two register type operands: "/mov R1, R2/" For this purpose I assume that the instruction definition in the TargetInstrInfo.td file

Spills created at the end of the block (I assume you mean what fast regalloc does at -O0) are created long after instruction selection. In that case it sounds like your implementation of storeRegToStackSlot/loadRegFromStackSlot is broken -Matt On Tue, Oct 25, 2016 at 7:30 AM +0800, "Alex Susu via llvm-dev" <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>>

Hello. I have extended the BPF back end with vector registers (inspiring from Mips MSA) - something like this: def MSA128D: RegisterClass<"Connex", [v128i16], 32, (sequence "Wh%u", 0, 31)>; I also added vector store and load instructions in the style of Mips MSA - see

Hi All, I wrote a very crude and simple AsmParser for my backend. llvm-tablegen also generates asm-matcher .inc file without any error. I have included the .inc file in my class for AsmParser. However, while building llvm, in linking stage for LTO, i am getting error - undefined reference to functions - ComputeAvailableFeatures, MatchInstructionImpl, MatchRegisterName and

Add several .gitignore rules to various directories to ensure a clean worktree after a default build. Signed-off-by: Ramkumar Ramachandra <artagnon at gmail.com> --- Just cloned and built LLVM. This annoyed me. Here's a trivial patch. .gitignore | 10 ++++++++++ bindings/ocaml/llvm/.gitignore | 1 + docs/.gitignore

variable_ops is used in the tablegen defs for many targets to denote instructions that a variable number of inputs, but it seems that there aren't any targets for which this results in variable elements in the instruction encoding (and thus in assembler parsing), since the tablegen generated assembly matcher ($(Target)GenAsmMatcher.inc) simply assumes that variable_ops are not to be parsed

Hello. I wanted to inform that I fixed the bug from the previous email. The main reason for the bug was that I thought that the SDNode masked_gather is returning only 1 value, but it returns 2 (hence, I guess, the earlier reported, difficult to follow, error: "Assertion `New->getNumTypes() == 1"). masked_gather returns 2 values because: // SDTypeProfile -

Hi Alex, So far, the code you've mentioned only defines a couple tablegen classes but doesn't define the instruction itself. To define the instruction you will also need a 'def' statement. For MIPS MSA, this statement looks like this: def LD_D: LD_D_ENC, LD_D_DESC; This defines an instruction (LD_D) with the encoding specified by the LD_D_ENC class, and the operation

Hello, I'm trying to define in my new back end, in MyBackendInstrInfo.td file, a vector load instruction that takes an immediate address operand. (I got inspired from Mips' MSA SIMD extensions.) Could you please tell me what's the right way to do it? Here, the load class has $addrsrc which is a relative address with base a certain register and offset: class