similar to: [LLVMdev] Question about isel patterns

Displaying 20 results from an estimated 200 matches similar to: "[LLVMdev] Question about isel patterns"

2012 Jan 18
0
[LLVMdev] Question about isel patterns
On Tue, Jan 17, 2012 at 7:04 PM, Akira Hatanaka <ahatanak at gmail.com> wrote: > I am looking for a way to define patterns without specifying the type > of the root node in the RHS result. > I want to be able to write something like this: > > def : Pat<(i64 imm:$in), (GenDAG imm:$in)>; > (GenDAG is a custom function that returns the DAG that replaces the > node in
2013 Apr 01
3
[LLVMdev] proposed change to class BasicTTI and dual mode mips16/32 working
On Thu, Mar 28, 2013 at 12:22 PM, Nadav Rotem <nrotem at apple.com> wrote: > IMHO the right way to handle target function attributes is to > re-initialize the target machine and TTI for every function (if the > attributes changed). Do you have another solution in mind ? I don't really understand this. TargetMachine and TTI may be quite expensive to initialize. Doing so for
2007 Jul 12
1
[LLVMdev] backend problem with LiveInterval::removeRange
Hi all, When compiling some programs using the Mips backend i'm getting this assert message on lib/CodeGen/LiveInterval.cpp:227: "Range is not entirely in interval!" I don't know yet if it's something that is missing on the backend code or why the range to be removed it outside the interval, does anyone have any clue? A more detailed output is attached. The program i tried
2017 Feb 04
0
[PATCH] ipconfig: handle multiple interfaces correctly
When configuring multiple interfaces, the existing logic in ipconfig can fail if DHCP replies are received out of the expected order, or if one or more interfaces never receive replies. The current ipconfig logic uses a single packet socket to handle all incoming DHCP replies. If, for example, the host has two interfaces, A and B, and only B will be sent a DHCP reply, the order of events goes
2019 Jan 18
0
[klibc:master] ipconfig: handle multiple interfaces correctly
Commit-ID: 31810c21e6e7ee7c0478e80cee35b0b7e51de826 Gitweb: http://git.kernel.org/?p=libs/klibc/klibc.git;a=commit;h=31810c21e6e7ee7c0478e80cee35b0b7e51de826 Author: Jay Vosburgh <jay.vosburgh at canonical.com> AuthorDate: Fri, 3 Feb 2017 16:36:51 -0800 Committer: Ben Hutchings <ben at decadent.org.uk> CommitDate: Wed, 2 Jan 2019 02:23:46 +0000 [klibc] ipconfig: handle
2010 Apr 26
1
valgrind ipconfig work
this is just on the common path, need to checkout others too, but a start: commit 5501109f6597f2bbed17a264b247c36220362dfb Author: maximilian attems <max at stro.at> Date: Mon Apr 26 08:07:51 2010 +0200 [klibc] ipconfig: Fix valgrind errors valgrind was rightfully complaining on ipconfig eth0: ERROR SUMMARY: 5 errors from 4 contexts (suppressed: 0 from 0) all
2012 Dec 28
1
[LLVMdev] [PATCH] LLVM build failure on OpenBSD/mips64
I'm just passing this patch on to the list as I know Brian is busy and I had proded him to file the bug report. http://llvm.org/bugs/show_bug.cgi?id=14721 "binutils on OpenBSD is quite old, which causes the build on mips64el to fail on MipsJITInfo.cpp - it complains of illegal operands. The attachment patches it so that it will build. All the patch does is replace the register aliases
2016 Oct 15
3
How to remove memcpy
Hi, I am hoping that someone can help me figure out how to prevent the insertion of "memcpy" from the assembly source. My target is an instruction set simulator that doesn't support this. Thank you for your valuable time. Wolf *Here are my compile commands:* $ clang -emit-llvm -fno-builtin -o3 --target=mips -S matrix_float.c -o vl_matrix_float.ll $ llc vl_matrix_float.ll *IR
2013 Feb 20
0
[LLVMdev] Is va_arg correct on Mips backend?
Does it make a difference if you give the "-target" option to clang? $ clang -target mips-linux-gnu ch8_3.cpp -o ch8_3.bc -emit-llvm -c The .s file generated this way looks quite different from the one in your email. On Tue, Feb 19, 2013 at 5:06 PM, Jonathan <gamma_chen at yahoo.com.tw> wrote: > I didn't have Mips board. I compile as the commands and check the asm >
2013 Feb 28
0
[LLVMdev] Mips backend 3.2 va_arg possible bug
Could you file a bug? On Wed, Feb 27, 2013 at 2:47 AM, Stavropoulos Nikos < n.stavropoulos at think-silicon.com> wrote: > i have this code > > typedef long long L; > typedef integer I; > void test2(auto L p0, auto L p1, auto L p2, auto L p4, ...) > { > va_list select; > > va_start (select, p4); > > report( va_arg(select,L) ); > report(
2013 Feb 20
3
[LLVMdev] Is va_arg correct on Mips backend?
I didn't have Mips board. I compile as the commands and check the asm output as below. 1. Question: The distance of caller arg[4] and arg[5] is 4 bytes. But the the callee get every arg[] by 8 bytes offset (arg_ptr1+8 or arg_ptr2+8). I assume the #BB#4 and #BB#5 are the arg_ptr which is the pointer to access the stack arguments. 2. Question: Stack memory 28($sp) has no initial value. If
2013 Feb 27
2
[LLVMdev] Mips backend 3.2 va_arg possible bug
i have this code typedef long long L; typedef integer I; void test2(auto L p0, auto L p1, auto L p2, auto L p4, ...) { va_list select; va_start (select, p4); report( va_arg(select,L) ); report( va_arg(select,I) ); report( va_arg(select,L) );
2013 Oct 03
1
[LLVMdev] Help with a Microblaze code generation problem.
Sorry if this is a duplicate: I tried to send it last night and it didn't go through. I'm trimming some text to see if it helps. I have a simple program that fails on the Microblaze: int main() { unsigned long long x, y; x = 100; y = 0x8000000000000000ULL; return !(x > y); } As you can see, the test case compares two unsigned long long values. To try to track
2011 Mar 28
5
[PATCH 1/3] Only peek and discard packets from specified device.
This patch fixes a bug on systems with multiple connected network devices. As packet_peek uses all devices to receive data instead of a specific device. As the return value was never reset it was possible that packets from other devices were returned by packet_peek. That means that the ifindex did not match any ifindex of the specified devices the packet was never removed and packets for the
2010 Jul 07
0
[git pull v2] x86_32, sh4, getrusage()
hello hpa, here my birthday submission :) please pull: git pull git://git.debian.org/users/maks/klibc.git maks Sam fixed a longstanding x86_32 build bug, thus it seems a good time to flush the queue of the piled up patches, the shortlog tells it: Aurelien Jarno (1): [klibc] sh4: syscalls fixes Benjamin Cama (1): [klibc] fstype: btrfs size endianness fix Mike Waychison (2):
2005 Jan 24
0
AW: sshd hangs
hello applied the patch described below - unfortunately we still experience rare hangs of the remote sshd. not surprising as the patch only changes a few lines in server_loop() - but not in server_loop2() which i used for non-interactive sessions. process id of hanging sshd: 26110 process is sleeping forever in poll (why does server_loop2() sleep forever?): root at XXX:~# truss -fp 26110 26110:
2003 Apr 29
0
[PATCH] Fix busy-looping behaviour in ipconfig
The ipconfig code does not drop incoming packets that it can't handle. Since the packet socket sends ipconfig its own broadcast requests, ipconfig has the unfortunate behaviour of eating 100% of the CPU time when it does not receive an immediate response to its outgoing requests. This patch fixes the problem, by ensuring that packets are dropped if they are not handled. It also introduces a
2012 Nov 11
2
[LLVMdev] Tracing nodes in selectionDAG to final code...
Hello everyone. I use this command clang -emit-llvm hello.c -c -o hello.bc llc hello.bc -march=mipsel -relocation-model=static -o hello.s to produce this MIPS code: .section .mdebug.abi32 .previous .file "hello.bc" .text .globl main .align 2 .type main, at function .set nomips16 # @main .ent main main: .cfi_startproc .frame $sp,32,$ra .mask 0x80000000,-4 .fmask
2013 Apr 02
0
[LLVMdev] Target Instructions
Hello, Considering the following MachineInstruction dumped by some SUnit for MIPS target in PostRA-Scheduling “%A1<def> = ADDiu %ZERO, 30”, and the format for the ADDiu instruction is ADDiu rt, rs, immediate. The encoding for the instruction is 001001 rs rt immediate, with lengths of 6, 5, 5, 16 respectively. My question is how to map the operands with their right register? i.e. %A1 = rt,
2013 Sep 02
0
[LLVMdev] .globl
Hi Reed, Still catching up on email, so hope this isn't already covered... reed kotler <rkotler at mips.com> writes: > I have a strange issue that I encountered with mips16 hard float. > > Part of mips16 hard float is to emit calls to runtime routines with the > same signature as usual soft float routines, except that they are > implemented using mips32 code which uses