similar to: [LLVMdev] [RFC] Extending MachineInstr.Flags

Hi Jim. I'm doing custom lowering but here I have a very basic issue and the situation is like this - [Original Op] Mul Dest, Src1, Src2 [Expanded from EmitInstrWithCustomInserter] Step1 Dest, Src1, Src2    <=== BuildMI(..., Step1, Dest).addReg(Src1).addReg(Src2) Step2 Dest, Src1, Src2    <=== BuildMI(..., Step2, Dest).addReg(Src1).addReg(Src2) Step3 Dest, Src2, Src1    <===

Hi, Jim. In my case the target (Tilera) doesn't have a full 32-bit mult operation and to do so it has to accumulate results from three 16-bit mults, by retaining operands and the result across in the same registers. However the ISel DAG thinks its a CSE case. Please note this is not a MAdd/MSub triad. How could I do this by defining such a sequence or the pattern in the .def file itself for

Ah, OK. I think I understand much better now. Thanks! You shouldn't need bundles for that sort of thing. A custom lowering or a fancy pattern should be sufficient, depending on the details of how your target is defined. For patterns, looks at the various targets use of the Pat<>, Pattern<>, ComplexPattern<> and related classes in the .td files. For examples of custom

Hello All. On a particular target the back-end generates an instruction like: beqz      r2, "$BB0_-1"   Is it a back-end specific issue? Could someone please help me figure out how this gets resolved? What confuses me is, all other branches are correctly labelled and resolved!  Thanks. Girish. -------------- next part -------------- An HTML attachment was scrubbed... URL:

May be you have branched to a BB which has been deleted. On 24 January 2012 20:16, girish gulawani <girishvg at yahoo.com> wrote: > > Hello All. > On a particular target the back-end generates an instruction like: > beqz r2, "$BB0_-1" > > Is it a back-end specific issue? Could someone please help me figure out > how this gets resolved? What confuses me

Hi Girish, Sorry, but I'm afraid I don't understand your question. Can you elaborate a bit? -Jim On Dec 19, 2011, at 9:12 PM, girish gulawani wrote: > > Hello Jim. > Just out of curiosity, won't such mechanism work via the patterns from instructions defs? > > Thanks. > Girish. > > From: Jim Grosbach <grosbach at apple.com> > To: Johannes

Hello Jim. Just out of curiosity, won't such mechanism work via the patterns from instructions defs? Thanks. Girish. >________________________________ > From: Jim Grosbach <grosbach at apple.com> >To: Johannes Birgmeier <e0902998 at student.tuwien.ac.at> >Cc: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> >Sent: Monday, 19 December 2011 10:33 PM

  Hi Aries. Thanks very much! Precisely this is the situation! There're two consecutive branches (br1cond and br2uncond). Inside of AnalyzeBranch, there's an opcode swap of br2uncond (ex. j_foward to j_backward). There I do BuildMI (newOpcode) and followed by br2uncond->eraseFromParent(). This results in br1cond loosing it's label/offset. How could I resolve this? Best regards,

On Jan 3, 2012, at 5:45 PM, Joe Abbey wrote: > What a shame. Any chance of getting his slides posted? The odds are pretty good, I just uploaded them :) -Chris

Hello Chris. Can you please provide the URL where the slides are uploaded? Thanks. Girish. >________________________________ > From: Chris Lattner <clattner at apple.com> >To: Joe Abbey <jabbey at arxan.com> >Cc: "llvmdev at cs.uiuc.edu List" <llvmdev at cs.uiuc.edu> >Sent: Thursday, 5 January 2012 6:27 AM >Subject: Re: [LLVMdev] LLVM Dev Meeting

Hi Evan. The hasSideEffects method I believe operates only on Inline Assembly (IA) blocks. What if such a sequence is not part of IA? Thanks. Girish. If an instruction is marked as side-effect free then it's a candidate for CSE. Try marking the instruction with hasSideEffects. > >Evan > >On Dec 17, 2011, at 12:24 PM, Johannes Birgmeier wrote: > >> Hello, >>

Hi, I am not able to find the documentation on SPEDI. Or the source code for the project. Thanks and Regards, Tarun. On Mon, Jan 9, 2012 at 3:24 PM, girish gulawani <girishvg at yahoo.com> wrote: > > > Hello Tarun. > You mean SPEDI? > http://llvm.org/ProjectsWithLLVM/2003-Fall-CS497YYZ-SPEDI.pdf > > Regards, > Girish. > > *From:* tarun agrawal <tarun

Hello LLVM, I'd like to check TSFlags in my AsmBackend code. However AsmBackend objects don't have a reference to MCInstrInfo, which is the only way I've seen to reach TSFlags. A quickie grep shows that none of the existing targets check TSFlags in their AsmBackends. Is there any reason I shouldn't check TSFlags in AsmBackend? If not, what's the best way to go about it?

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Hi, I'd like to modify MachineBasicBlock contents within a MachineFunctionPass on the basis of how many CPU cycles the assembly instructions corresponding to the MBB take. I'm using the AVR backend and the number of CPU cycles every AVR assembly operation takes is openly available. Is there any straightforward way of getting the opcode mnemonics corresponding to a MachineInstr? I've

On 10/23/12 7:19 PM, Craig Topper wrote: > What function provides the encoding length? X86 in particular is so > difficult to encode that only the old style JIT and the MC Code > Emitter could possibly know how many bytes something takes. The getSize() method of MCInstrDesc which can be fetched from a MachineInstr using the getDesc() method:

Anyone using the penalised partial likelihood routines in survival5 should update their version. A bug has been fixed in the S package: in coxph() models with penalised likelihood and strata it was possible in some circumstances to get an infinite loop or perhaps an incorrect answer. The new version (2.3) is on cran.r-project.org and will percolate through CRAN in the next few days. -thomas

Anyone using the penalised partial likelihood routines in survival5 should update their version. A bug has been fixed in the S package: in coxph() models with penalised likelihood and strata it was possible in some circumstances to get an infinite loop or perhaps an incorrect answer. The new version (2.3) is on cran.r-project.org and will percolate through CRAN in the next few days. -thomas

What function provides the encoding length? X86 in particular is so difficult to encode that only the old style JIT and the MC Code Emitter could possibly know how many bytes something takes. On Tue, Oct 23, 2012 at 11:58 AM, John Criswell <criswell at illinois.edu>wrote: > Dear All, > > I'm enhancing a MachineFunctionPass that enforces control-flow integrity. > One of the

On Sat, 21 Aug 2004 ivo_welch-rstat8783@mailblocks.com wrote: > > peter/brian: thank you for the help. i can now report that gentoo > amd64 can compile R just fine, too; it requires the f77 USE flag and a > gcc compiler rebuild first, though. I also went to gcc 3.4.1. my > segfault troubles earlier were caused by my use of f2c. > > suggestion: would it be possible to