similar to: [LLVMdev] Contributing new backend to LLVM

On Tue, Nov 1, 2011 at 11:44 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: > Hello all, > > We would like to contribute a new backend for Qualcomm's Hexagon > processor.  We will actively maintain the port once it is accepted. > Hexagon is a VLIW core that is used principally in modem and low power > audio applications in Qualcomm's chip sets. > > We

On Nov 1, 2011, at 11:44 AM, Tony Linthicum wrote: > Hello all, > > We would like to contribute a new backend for Qualcomm's Hexagon > processor. We will actively maintain the port once it is accepted. > Hexagon is a VLIW core that is used principally in modem and low power > audio applications in Qualcomm's chip sets. > > We have a patch for both llvm and for

Eli, When you say "include tests" what exactly do you mean - ability to run newly produced binary on newly supported target? Can you please elaborate? Thanks. Sergei Larin -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Eli Friedman Sent: Tuesday, November 01, 2011 1:58 PM To: Tony Linthicum Cc: llvmdev at

On Tue, Jul 3, 2012 at 9:27 PM, Sebastian Pop <spop at codeaurora.org> wrote: > Hi, > > On Tue, Jul 3, 2012 at 9:48 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: >> On 7/3/2012 5:01 AM, Duncan Sands wrote: >>> Hi, >>> >>>> (4) llc -march=hexagon test.ll -o test.s >>>> >>>> '' is not a recognized

On 11/1/2011 3:46 PM, Chris Lattner wrote: > > If relevant, I'd suggest splitting it up as: > > 1. Changes to LLVM code outside your target directory. > 2. Your new target directory. > 3. Clang patches. > > As others have pointed out, you really do need some basic regression tests to make sure that the backend is working. Also, make sure to update this: >

On 7/3/2012 5:01 AM, Duncan Sands wrote: > Hi, > >> (4) llc -march=hexagon test.ll -o test.s >> >> '' is not a recognized processor for this target (ignoring processor) >> 0 llc 0x08c2512b >> Stack dump: >> 0. Program arguments: llc -march=hexagon test.ll -o test.s >> 1. Running pass 'Function Pass Manager' on module

Hey folks, We are having some difficulty with how we have been representing our predicate registers, and wanted some advice from the list. First, we had been representing our predicate registers as 1 bit (i1). The truth, however, is that they are 8 bits. The reason for this is that they serve as predicates for conditional execution of instructions, branch condition codes, and also as

On Tue, Feb 28, 2012 at 11:17 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: > Hey folks, > > We are having some difficulty with how we have been representing our > predicate registers, and wanted some advice from the list.  First, we > had been representing our predicate registers as 1 bit (i1).  The truth, > however, is that they are 8 bits.  The reason for this is

Hi, On Tue, Jul 3, 2012 at 9:48 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: > On 7/3/2012 5:01 AM, Duncan Sands wrote: >> Hi, >> >>> (4) llc -march=hexagon test.ll -o test.s >>> >>> '' is not a recognized processor for this target (ignoring processor) >>> 0 llc 0x08c2512b >>> Stack dump: >>> 0. Program

Hi Sebastian, On 19/07/12 05:57, Sebastian Pop wrote: > On Tue, Jul 3, 2012 at 9:27 PM, Sebastian Pop <spop at codeaurora.org> wrote: >> Hi, >> >> On Tue, Jul 3, 2012 at 9:48 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: >>> On 7/3/2012 5:01 AM, Duncan Sands wrote: >>>> Hi, >>>> >>>>> (4) llc -march=hexagon

Hi Eli, On Thu, Mar 1, 2012 at 2:21 PM, Eli Friedman <eli.friedman at gmail.com> wrote: > On Tue, Feb 28, 2012 at 11:17 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: >> Hey folks, >> >> We are having some difficulty with how we have been representing our >> predicate registers, and wanted some advice from the list.  First, we >> had been

Is there a VLIW support in LLVM? I found this, https://groups.google.com/forum/#!searchin/llvm-dev/VLIW, but it looks like it is not completely implemented. Specifically I'm interested in how instructions are bundled together. I can't seem to find it anywhere in the source code. Any help in resolving he issue is appreciated. -------------- next part -------------- An HTML attachment was

Kun, Thanks for the reply. I looked at it, but wasn't able to find where actual instruction bundling takes place, i.e. where exactly in the code they pack instruction into a single bundle. Do you know where it is done? I would really appreciate any pointers. Thanks. On Fri, Sep 25, 2015 at 4:37 PM, Kun Ling <kunling at lingcc.com> wrote: > Hi Rail, > For the VLIW support,

Thanks, Eric and Eli. We will do that, and will add some tests to include with our submission. We are also in the process of getting our simulator and C library (both proprietary) released under a new license so that folks can download them and actually run programs. That's a couple of months away, though, and doesn't really help much for creating LLVM regression tests. Still, it

Hi, It seems the only one VLIW target Hexagon in LLVM 3.2 devel uses a straightforward way to emit its VLIW-style asm codes. It uses a list scheduler to schedule on DAG and a simple packetizer to wrap the emitted asm instructions. Both scheduling and packetizing work on basic blocks. so, is there any plan to implement better optimization methods such as trace scheduling, software pipelining, ...

On Dec 12, 2011, at 2:41 PM, Eric Christopher wrote: > > On Dec 12, 2011, at 2:36 PM, Tony Linthicum wrote: > >> On 12/12/2011 4:28 PM, Jakob Stoklund Olesen wrote: >>> >>> >>> On Dec 12, 2011, at 2:12 PM, Tony Linthicum wrote: >>> >>>> Hi folks, >>>> >>>> I just committed a new backend for the Hexagon

On Dec 12, 2011, at 2:51 PM, Tony Linthicum wrote: > On 12/12/2011 4:49 PM, Eric Christopher wrote: >> >> >> On Dec 12, 2011, at 2:41 PM, Eric Christopher wrote: >> >>> >>> On Dec 12, 2011, at 2:36 PM, Tony Linthicum wrote: >>> >>>> On 12/12/2011 4:28 PM, Jakob Stoklund Olesen wrote: >>>>> >>>>>

On 12/12/2011 4:28 PM, Jakob Stoklund Olesen wrote: > > On Dec 12, 2011, at 2:12 PM, Tony Linthicum wrote: > >> Hi folks, >> >> I just committed a new backend for the Hexagon processor. After >> committing, I was able to successfully check out, build and test with >> the new changes. The x86_64 build on the buildbot is failing, >> however.

Hi all, I'd recommend Andy Trick be made code owner of "instruction scheduling" (including MI, pre-RA, and post-RA schedulers). I am also recommending Nadav Rotem be made code owner of "loop vectorizer". Evan

Hi paulr, Thank you for your response :) Hi Krzysztof, This is really helpful! Thank you for your guidance!! I would like to trace the Hexagon's llvm implementation. I am very interested on how Hexagon implement instruction pattern matching, instruction scheduling, and register allocation, could you give me some suggestions or reading lists to help me understand Hexagon's llvm