similar to: [LLVMdev] Problems with live intervals and spilling when having sub registers?

Hi Ehsan, In some cases modulo scheduling will insert copy instruction that end up as real copies in the final code. It unavoidable in some cases. For example, let's say a instruction defining a value is scheduled in the first iteration, but one of its uses is scheduled two iterations later. In this case, the kernel needs to create a copy because there will be two values live in the

Hi, I have come across a csmith generated test case that made the MachineVerifier spit out: *** Bad machine code: Multiple connected components in live interval *** Having looked at what this might mean, it seems that ConnectedVNInfoEqClasses::Classify() was called on the LI in question by the verifier, and that it returned two equivalence classes, instead of just one, which is demanded by

Hi Jonas, Could you file a PR with your test case please? Thanks, -Quentin > On Apr 16, 2015, at 3:50 PM, Andrew Trick <atrick at apple.com> wrote: > >> >> On Apr 16, 2015, at 6:58 AM, Jonas Paulsson <jonas.paulsson at ericsson.com <mailto:jonas.paulsson at ericsson.com>> wrote: >> >> Hi, >> >> I have come across a csmith generated

Hi Jonas, > On Apr 20, 2015, at 4:03 AM, Jonas Paulsson <jonas.paulsson at ericsson.com> wrote: > > Hi Quentin, > > After Simple Register Coalescing. Is the code you have pasted with the PHIs feed to the register coalescer? I am trying to understand the setting to help debugging the problem. Also, what does -debug-only=regalloc tell you? Thanks, -Quentin > >

Hi Quentin, On 08/19/14 18:58, Quentin Colombet wrote: [...] > It seems that you will have to debug further the *** Bad machine code: Instruction loads from dead spill slot *** before we can be of any help. Yes, I've done some more digging. Sorry for the long mail... I get: Inline spilling aN40_0_7:%vreg1954 [5000r,5056r:0)[5056r,5348r:1) 0 at 5000r 1 at 5056r At this point I have

Hi Jonas, When is the MachineVerifier complaining? I mean after which pass? Thanks, -Quentin > On Apr 17, 2015, at 7:17 AM, Jonas Paulsson <jonas.paulsson at ericsson.com> wrote: > > Hi, > > thanks for answering, but the COPY is there already from after isel. It is a copy of a subreg, after a a call returning 64 bits. > > call

Hello, I noticed the following interesting code sequence while compiling a piece of code with the backend I'm developing. Probably this issue is for Jakob, but anyways this is what I'm getting: STDWPtrQRr <fi#12>, 0, %R25R24; mem:ST2[FixedStack12](align=1) STDWPtrQRr <fi#12>, 0, %R25R24; mem:ST2[FixedStack12](align=1) STDWPtrQRr <fi#13>, 0, %R23R22;

On Jan 27, 2012, at 10:20 AM, Borja Ferrer wrote: > Hello, > > I noticed the following interesting code sequence while compiling a piece of code with the backend I'm developing. Probably this issue is for Jakob, but anyways this is what I'm getting: > > STDWPtrQRr <fi#12>, 0, %R25R24; mem:ST2[FixedStack12](align=1) > STDWPtrQRr <fi#12>, 0, %R25R24;

Hi, I have a problem in our 3.0-based backend that I'm not sure how it should be handled. In summary, I don't know if * The regalloc verifier is too picky? * The register allocator is at fault for spilling the full register when only parts of it are defined? * Something else? The architecture I'm compiling for has registers with three disjoint parts: g, h and l. In one function we

Hi, I get strange code when using regalloc=greedy. A value spill is redundant and cleared, as another spill of same value is inserted. The former spill is however not NOP:ed, but KILL:ed, thus the operands get a kill status. The code becomes: %vreg301<def> = mv32Imm 200000000, pred:0, pred:%noreg, %CCReg<imp-def,dead>, %ac0<imp-use>, %ac1<imp-use>; aN32_0_7:%vreg301

Hi, I have a problem regarding sub-register definitions and LiveIntervals on our target. When a subregister is defined, other parts of the register are always left untouched - they are neither read or def:ed. It however seems that Codegen treats subregister definitions as somehow clobbering the whole register. The SSA-code looks like this after isel: (Reg0 and Reg1 are 16bit registers. Reg2,

I am trying to use ChanIsAvail to detect the best route for a call. I am testing by dialing an extension that is then forwarded to the DID. Normally it will be an incoming PSTN call that is forwarded. When I try it, I get put on hold for a few seconds and miss the beginning of the recorded message. Any ideas what is going on? -- Executing ChanIsAvail("SIP/501-304d",

I have a server that is not replicating correctly, but passes all the tests listed here: https://wiki.samba.org/index.php/Samba4/HOWTO/Join_a_domain_as_a_DC In particular running # host -t CNAME 976c9c86-288d-483e-baec-7043a9c4a6cd._msdcs.ncs.k12.de.us 976c9c86-288d-483e-baec-7043a9c4a6cd._msdcs.ncs.k12.de.us is an alias for ncssamba2.ncs.k12.de.us. returns correct information on all DCs.

Hi Quentin, On 08/15/14 19:01, Quentin Colombet wrote: [...] >> The question is: How should true subregister definitions be >> expressed so that they do not interfere with each other? See the >> detailed problem description below. > > We do have a limitation in our current liveness tracking for > sub-register. Therefore, I am not sure that is possible. > >

Hi - I replied to the original sender only by mistake. Sorry about that. When we started working on the pipeliner, and added it before the scheduler, we also were concerned that the scheduler or other passes would undo the work of the pipeliner. The initial thought was that we would add information (using metadata or some other way like you've suggested) to the basic block to tell the

Hi, While working on adding newlib to my backend I hit the following assert : Assertion failed: BestRC && "Couldn't find the register class", file TargetRegisterInfo.cpp, line 112 The following llvm causes this : define void @specialBreak(i8* %out) nounwind { entry: %out.addr = alloca i8*, align 4 store i8* %out, i8** %out.addr, align 4 %0 = load i8** %out.addr,

Adding some links to links.html --- images/hw/pioneer_c.png | Bin 0 -> 3389 bytes images/hw/tesla.png | Bin 0 -> 6145 bytes links.html | 13 +++++++++++++ 3 files changed, 13 insertions(+) create mode 100644 images/hw/pioneer_c.png create mode 100644 images/hw/tesla.png diff --git a/images/hw/pioneer_c.png b/images/hw/pioneer_c.png new file mode 100644 index

I'm able to do this as follows, but am wondering if anyone knows a simpler way which still avoids explicit loops? > (mystring <- letters[1:5]) [1] "a" "b" "c" "d" "e" > unlist(sapply(mystring[-length(mystring)], + function(x) paste(x,mystring[(grep(x,mystring)+1):length(mystring)],sep=""))) a1 a2 a3

How can I look up the aspect ratio of a plot, so I can use that to correctly adjust the angle of text which is supposed to be parallel to a line in the plot? The following example code works for a 1:1 aspect ratio, but puts the text at the wrong angle if the plot region is short and wide or tall and narrow. I can't find a par() component containing the plot aspect ratio. It will be for

The order() function allows you to specify multiple vectors, which are used successively to break ties. If I want to use many vectors to break ties (say, 25 or more), that are columns of a matrix or elements of a list, does anyone know a shortcut to do this without passing 25 arguments to order()? -- Levi Waldron post-doctoral fellow Jurisica Lab, Ontario Cancer Institute Division of Signaling