similar to: [LLVMdev] TIlera backend in LLVM

On Wed, Sep 05, 2012 at 07:48:48PM +0200, JUHASZ David wrote: > Hi, > > I would like to inform the community that I'm releasing the backend for > tile64 I developed in the past several months. It can be downloaded from > > http://pnyf.inf.elte.hu/juhda/projects/tilera/ > > The version for LLVM 3.1 is a minimalist functioning implementation. Now > I am working on

Hi, I would like to inform the community that I'm releasing the backend for tile64 I developed in the past several months. It can be downloaded from http://pnyf.inf.elte.hu/juhda/projects/tilera/ The version for LLVM 3.1 is a minimalist functioning implementation. Now I am working on utilizing the VLIW packetizer of LLVM, and other improvements are planned for the future. I would be

----- Original Message ----- > From: "Jiong Wang" <jiwang at tilera.com> > To: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>, cfe-dev at cs.uiuc.edu > Sent: Thursday, February 28, 2013 6:09:20 PM > Subject: [LLVMdev] RFC: TileGX, a new backend for Tilera's many core processor > > Hi, > > On behalf of Tilera Corporation,

On 03/08/2013 04:48 AM, Dmitri Gribenko wrote: > On Thu, Mar 7, 2013 at 6:33 PM, Jiong Wang <jiwang at tilera.com> wrote: >> Hi all, >> >> Updated the patches for TILE-Gx backend: >> >> 1. added initial regression tests for tilegx codegen. >> 2. added initial regression tests for MC Layer. >> 3. fixed those commenting style issues. >>

On 03/01/2013 10:42 PM, Hal Finkel wrote: > > As some of the llvm modules are in active development, for example MC > Layer, we want to return code to community repository first, so that > it will be easy to keep pace with llvm main tree. > I think this makes sense; but my impression is that the community will want a clear idea that this will be maintained and improved for the

Hi ML readers, I would first apology if this was already addressed on this ML, but I didn't find information on this topic. I would like to add custom pragma's that generate particular LLVM IR. Here is an example: int a, b; /* ... */ #pragma mypragma shared(a, b) { a = b; b++; } would result in this (pseudo) LLVM IR: %1 alloca i32 %2 alloca i32 ... call void

----- Original Message ----- > From: "Jiong Wang" <jiwang at tilera.com> > To: "Hal Finkel" <hfinkel at anl.gov> > Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>, cfe-dev at cs.uiuc.edu > Sent: Friday, March 1, 2013 1:34:15 AM > Subject: Re: [LLVMdev] RFC: TileGX, a new backend for Tilera's many core processor >

Hi, On behalf of Tilera Corporation, I'd like to contribute llvm ports to Tilera's TILE-Gx architecture and wish this could be submitted to main llvm tree. TILE-Gx is a VLIW architecture with 64-bit registers, 64-bit address space, and 64-bit instructions. TILE-Gx has load-store architecture ISAs. More information on the architectures is available at

On Mar 8, 2013, at 2:31 AM, Jiong Wang <jiwang at tilera.com> wrote: > On 03/08/2013 04:48 AM, Dmitri Gribenko wrote: >> On Thu, Mar 7, 2013 at 6:33 PM, Jiong Wang <jiwang at tilera.com> wrote: >>> Hi all, >>> >>> Updated the patches for TILE-Gx backend: >>> >>> 1. added initial regression tests for tilegx codegen. >>>

Hi all, Updated the patches for TILE-Gx backend: 1. added initial regression tests for tilegx codegen. 2. added initial regression tests for MC Layer. 3. fixed those commenting style issues. please review, thanks. I have tried to understand the new backend requirement for LLVM from the mailiing list archive, it's sure TILE-Gx backend will be actively maintained & improved, it's

On Thu, Mar 7, 2013 at 6:33 PM, Jiong Wang <jiwang at tilera.com> wrote: > Hi all, > > Updated the patches for TILE-Gx backend: > > 1. added initial regression tests for tilegx codegen. > 2. added initial regression tests for MC Layer. > 3. fixed those commenting style issues. > > please review, thanks. This is a huge patch, and reviewing it in tar.gz is hard. To

On Fri, Mar 1, 2013 at 4:52 PM, Jiong Wang <jiwang at tilera.com> wrote: > On 03/01/2013 10:42 PM, Hal Finkel wrote: >> >> >> As some of the llvm modules are in active development, for example MC >> Layer, we want to return code to community repository first, so that >> it will be easy to keep pace with llvm main tree. >> I think this makes sense; but

On 03/02/2013 04:50 AM, Dmitri Gribenko wrote: > You also need tests for Clang bits, too. > > Mechanical issues: > > +/// getTileRegisterNumbering - Given the enum value for some register, > +/// return the number that it corresponds to. > > Please don't duplicate function and class name in comments. Existing > code does this, but current style guidelines advise not

On 03/01/2013 02:57 PM, Hal Finkel wrote: Hi Hal, thanks for feedback. > Jiong, I am happy to see the Tile backend being offered for upstream inclusion. Among other things, in the long run, this may help inform and motivate many-core capabilities in LLVM. > > First, can you elaborate on the future maintenance and development plans for the target code? Do you plan to add SIMD support?

on 2013/3/23 1:52, Chris Lattner wrote: > On Mar 19, 2013, at 8:58 PM, Jiong Wang <jiwang at tilera.com> wrote: > >> Hi Chris, >> >> could you please comment on committing TILE-Gx backend into community? > Hi Jiong, > > I don't have any special advice here. It sounds like the general functionality level is high enough. Taking it into mainline sounds

Hi Brian, Thanks for sharing your experience with dragonegg. I would like to use tilera-gcc as the compiler driver. native gcc would not be able to handle things like tilera specific intrinsics in the source code. I built dragonegg using GCC=/path/to/tilera-gcc48/bin/tile-gcc LLVM_CONFIG=/path/to/tilera-llvm/bin/tilegx-llvm-config make and also tried only emitting the IR

On Mar 19, 2013, at 8:58 PM, Jiong Wang <jiwang at tilera.com> wrote: > Hi Chris, > > could you please comment on committing TILE-Gx backend into community? Hi Jiong, I don't have any special advice here. It sounds like the general functionality level is high enough. Taking it into mainline sounds great, so long as it is reviewed by someone. -Chris > > >

No. The gcc cross compiler being used (tilera-gcc) is indeed 64-bit. Thanks On Tue, Oct 28, 2014 at 11:01 AM, Anton Korobeynikov < anton at korobeynikov.info> wrote: > Looks like your gcc is 32-bit and you're trying to load 64-bit plugin. > > On Tue, Oct 28, 2014 at 8:27 PM, Ajay Panyala <ajay.panyala at gmail.com> > wrote: > > Hi Brian, > > > >

于 2013/3/24 0:07, Joerg Sonnenberger 写道: > On Sat, Mar 23, 2013 at 04:59:49PM +0100, Tobias Grosser wrote: >> With Chris's reply you also got the general OK to upstream the >> patch, _AFTER_ the actual patches have been reviewed. > One thing I was asking on IRC for is whether it makes sense for new > backends to be committable in incremental steps. Especially for a >

Hi Chris, could you please comment on committing TILE-Gx backend into community? ========== TILE-Gx Status =========== Features Supported === 1. general function. 2. PIC/TLS/JumpTable. 3. Instructoin Bundling for VLIW. 4. Asm Parser 5. MC Layer (aware of instruction bundle), MCJIT support. 6. Initial regression tests for CodeGen & MC Layer. Regression Result === Expected Passes : 13363