similar to: [LLVMdev] Expected behavior of eliminateFrameIndex() on dbg_value machine instructions

On 10/10/11 19:19, Jakob Stoklund Olesen wrote: > On Oct 10, 2011, at 10:26 AM, Richard Osborne wrote: >> I'm investigating a bug associated with debug information that manifests >> itself in the XCore backend (PR11105). I'd like to understand what the >> expected behavior of eliminateFrameIndex() is when it is called on a >> dbg_value machine instruction. >

On Oct 10, 2011, at 10:26 AM, Richard Osborne wrote: > I'm investigating a bug associated with debug information that manifests > itself in the XCore backend (PR11105). I'd like to understand what the > expected behavior of eliminateFrameIndex() is when it is called on a > dbg_value machine instruction. That is up to the target. The TII::emitFrameIndexDebugValue() hook is

Hi, I have a case that is causing me grief in the form of an assert. The prolog Epilog inserter tries to remove Frame Index references. I have a DBG_VALUE instruction that looks like this (alongwith the Frame Index). This is for the Hexagon backend. ************************** fi#2: size=4, align=4, at location [SP-84] DBG_VALUE <fi#2>, 0, !"fooBar"; line no:299

Hello LLVM, The ARM target sometimes adds an instruction with a virtual register in eliminateFrameIndex(): https://github.com/llvm-mirror/llvm/blob/master/lib/Target/ARM/ARMBaseRegisterInfo.cpp This looks late for a virtual register to appear. Where is this vreg made real? Thanks, -steve

On 1/29/15 2:00 PM, Steve King wrote: > Hello LLVM, > The ARM target sometimes adds an instruction with a virtual register > in eliminateFrameIndex(): > > https://github.com/llvm-mirror/llvm/blob/master/lib/Target/ARM/ARMBaseRegisterInfo.cpp > > This looks late for a virtual register to appear. Where is this vreg made real? The register scavenger should take care of such

Hi! I started writing a LLVM backend for a custom architecture. I have some register and instruction .td files and some other files/classes like a MCStreamer for assembler output. At the moment I can compile some empty programs so far. I implemented the method ::eliminateFrameIndex() similar to the Sparc and ARM backend. The method looks like this: // frame pointer is in reg of class

----- Original Message ----- > From: "Steve King" <steve at metrokings.com> > To: jonathan at codesourcery.com > Cc: llvmdev at cs.uiuc.edu > Sent: Friday, January 30, 2015 10:52:19 AM > Subject: Re: [LLVMdev] creating a vreg in eliminateFrameIndex() > > Thanks Jon and Hal for the helpful pointers. By returning true from > requiresRegisterScavenging() and

On Fri, Jan 30, 2015 at 8:59 AM, Hal Finkel <hfinkel at anl.gov> wrote: >> When the scavenged register is loaded with a simple immediate, is it >> safe to search the BB and replace other uses of the same immediate >> with the reg? In my case this gives a code size reduction. The >> search would stop on finding another use of the scavenged register. > > Are you

Hello all, For my custom processor backend I am trying add some instruction using BuildMI() inside eliminateFrameIndex(). I tried RegScavenger like this: unsigned RegUnused0 = RS->FindUnusedReg(&LASER::GNPRegsRegClass); if (!RegUnused0) RegUnused0 = RS->scavengeRegister(&LASER::GNPRegsRegClass, II, SPAdj); assert(RegUnused0 && "Register scavenger failed");

Thanks Jon and Hal for the helpful pointers. By returning true from requiresRegisterScavenging() and requiresFrameIndexScavenging(), LLVM handled all the scavenging effort. That is nearly painless for the target, so why do some targets seem to do scavenging on their own? When the scavenged register is loaded with a simple immediate, is it safe to search the BB and replace other uses of the same

The docs for the above-mentioned function say: This method may modify or replace the specified instruction, as long as it keeps the iterator pointing the the finished product. What does it mean to "keep an interator". Was "invalidates the iterator" intended, so something else. Another question, is how do I really replace the instruction. The operator= is private

On Mar 7, 2012, at 5:19 PM, Pranav Bhandarkar <pranavb at codeaurora.org> wrote: > Hi, > > I have a case that is causing me grief in the form of an assert. The prolog > Epilog inserter tries to remove Frame Index references. I have a DBG_VALUE > instruction that looks like this (alongwith the Frame Index). This is for > the Hexagon backend. > **************************

I have a question regarding the DBG_VALUE instruction. IIUC the DBG_VALUE appears in two different forms: 1. DBG_VALUE( %Reg, %Reg, metadata) 2. DBG_VALUE(%Reg, offset, metadata) In the first version, the second operand is always a %noreg in the form of: DBG_VALUE(%Reg, %noreg, metadata). Is it possible to have a different version of DBG_VALUE that only has 2 operands which will have only

+llvmdev -llvm-commits Hi! I've got the following questions about DBG_VALUE instruction: 1) When I dump this instruction I see the line of the form: DBG_VALUE %EDI, 0, !"a"; line no:47 for two completely different cases: * when value of "a" is actually stored in a register %edi (this should be encoded as "DW_OP_reg5" in DWARF). * when value of

Hi Jonas, Thanks for starting the discussion here. I am going to update the subject line some people might overlook it otherwise. I have a few thoughts which I have highlighted below. > -----Original Message----- > From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Jonas Paulsson > via llvm-dev > Sent: Friday, May 4, 2018 2:57 AM > > Hi, > > I

Hi again, Here is a small patch to fix this issue. Please note that since the problem results in broken bundles, it can result in invalid schedules for any VLIW back-ends using bundling to group instructions. Best regards Saurabh Verma From: Verma, Saurabh Sent: Tuesday, December 19, 2017 4:14 PM To: llvm-dev at lists.llvm.org Subject: DBG_VALUE insertion for spills breaks bundles Hi, The

Thanks Adrian. I will do the needful. Best regards Saurabh -------------------------------------------------------------- Intel Research and Development Ireland Limited Registered in Ireland Registered Office: Collinstown Industrial Park, Leixlip, County Kildare Registered Number: 308263 This e-mail and any attachments may contain confidential material for the sole use of the intended

Hi, The insertion of DBG_VALUE instructions for spills does not seem to be handling insert locations inside bundles well. If the spill instruction is part of a bundle, the new DBG_VALUE is inserted after it, but does not have the bundling flags set. This essentially means that if we start with a set of bundled instructions: MI1 [BundledSucc=true, BundledPred=false] MI2 [BundledSucc=false,

What program did you use to test the feature, and what was missing information? I'd like to file that as a bug so that we can fix this later. On Thu, Mar 16, 2017 at 2:34 PM, David Blaikie <dblaikie at gmail.com> wrote: > FWIW - selfhosting I did find that GDB wasn't able to find the source code > for some functions when using LLD's gdb_index, so I've switched back to

> I don't see how this is a meaningful distinction in LLVM IR. In LLVM IR we only have SSA values. An SSA value could be an alloca, or a gep into an alloca, or spilled onto the stack at the MIR level, in which case the dbg.value should get lowered into a memory location (if it isn't explicitly a DW_OP_stack_value). I think the distinction is still important; even at the IR level, if we