similar to: [LLVMdev] [RFC] LegalizeDAG support for targets without subword load/store instructions

On 16 Jul 2011, at 03:34, Matt Johnson wrote: > Hi All, > Some targets don't provide subword (e.g., i8 and i16 for a 32-bit > machine) load and store instructions, so currently we have to > custom-lower Load- and StoreSDNodes in our backends. For examples, see > LowerLOAD() and LowerSTORE() in {XCore,CellSPU}ISelLowering.cpp. I > believe it's possible to

Hi Eli, On 07/27/2011 04:59 PM, Eli Friedman wrote: > On Wed, Jul 27, 2011 at 2:28 PM, Matt Johnson > <johnso87 at crhc.illinois.edu> wrote: >> Hi All, >> I'm writing a backend for a target which only supports 4-byte, >> 4-byte-aligned loads and stores. I custom-lower all {*EXT}LOAD and >> STORE nodes in TargetISelLowering.cpp to take advantage of

On Wed, Jul 27, 2011 at 3:50 PM, Matt Johnson <johnso87 at crhc.illinois.edu> wrote: > Hi Eli, > > On 07/27/2011 04:59 PM, Eli Friedman wrote: >> >> On Wed, Jul 27, 2011 at 2:28 PM, Matt Johnson >> <johnso87 at crhc.illinois.edu>  wrote: >>> >>> Hi All, >>>     I'm writing a backend for a target which only supports 4-byte,

Hi, I have a question about implementing subword register allocation problems (see the REFERENCES in the end of this message) on LLVM. I have algorithms, but don't know the best way to implement them in LLVM. I asked similar question before: http://lists.cs.uiuc.edu/pipermail/llvmdev/2005- May/004001.html Because I still don't have a satisfying solution now, I try to elaborate it

Hi All, I'm writing a backend for a target which only supports 4-byte, 4-byte-aligned loads and stores. I custom-lower all {*EXT}LOAD and STORE nodes in TargetISelLowering.cpp to take advantage of all alignment information available to the backend, rather than treat each load and store conservatively, which takes O(10) instructions. My target's allowsUnalignedMemoryOperations()

On Wed, Jul 27, 2011 at 2:28 PM, Matt Johnson <johnso87 at crhc.illinois.edu> wrote: > Hi All, >     I'm writing a backend for a target which only supports 4-byte, > 4-byte-aligned loads and stores.  I custom-lower all {*EXT}LOAD and > STORE nodes in TargetISelLowering.cpp to take advantage of all alignment > information available to the backend, rather than treat each

I'm still trying to track down some alignment issues with loads(i.e. 8/16 bit loads being turned into 32bit sign extending loads) and I cannot for the life of me seem to figure out how to enter this section of code: // If this is an unaligned load and the target doesn't support it, // expand it. if (!TLI.allowsUnalignedMemoryAccesses()) { unsigned

In -help output, -help - Display available options (--help-hidden for more) Both single and double - option markers are accepted, which is good. It would probably be better to refer to options consistently using the single marker in all cases. =linearscan - linear scan register allocator =pbqp - PBQP

They looked real enough to me: /Volumes/mrs5/net/llvm/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp: In function ‘bool<unnamed>::isFPS16Immediate(llvm::ConstantFPSDNode*, short int&)’: /Volumes/mrs5/net/llvm/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp: 148: warning: dereferencing type-punned pointer will break strict- aliasing rules

Mon Ping, Thanks for the tip, but I can't for the life of me seem to get the Value from a StoreSDNode. From looking at the SelectionDAGNodes header file, the only class that has the getValue function call is SrcValueSDNode that returns a Value type. The only class that has getType is a ConstantPoolSDNode. I don't think that ConstantPoolSDNode is what I want and when I try to cast the

Hi Russell, I took care of these points except for > In -version output, > > Low Level Virtual Machine (http://llvm.org/): > llvm version 2.6svn > Optimized build. > Built Feb 14 2010(11:05:20). > > Registered Targets: > alpha - Alpha [experimental] > arm - ARM > bfin - Analog Devices Blackfin [experimental] > c - C

> I have installed LLVM on my machine (ubuntu) a while ago. I think my LLVM version is 2.8. is it supported in 2.8 ? When I install i didn't configure LLVM for mips. Do I have to configure it when I build ? I don't know what's the default llvm configuration for ubuntu! But you can check for mips support using "llc --version". Yes, it's supported in 2.8, although it

Ok. And what does llvm-gcc --version show? --- With best regards, Anton Korobeynikov On Mar 6, 2012 5:22 PM, "Rafael Parizi" <parizi.computacao at gmail.com> wrote: > > For compile and link Basicmath files (using shell script): > > llvm-gcc -emit-llvm basicmath_small.c -c -o basicmath_small.bc > llvm-gcc -emit-llvm cubic.c -c -o cubic.bc > llvm-gcc -emit-llvm

How do I access the address qualifier from the store instruction. Given the following code: define void @test_unary_op_anegate(float %x, float addrspace(11)* %result) nounwind { entry: %neg = sub float -0.000000e+000, %x ; <float> [#uses=1] store float %neg, float addrspace(11)* %result ret void } When I attempt to generate this code, I'm

I have installed LLVM on my machine (ubuntu) a while ago. I think my LLVM version is 2.8. is it supported in 2.8 ? When I install i didn't configure LLVM for mips. Do I have to configure it when I build ? Thanks in advance. Really appreciate it. --- On Thu, 9/1/11, Bruno Cardoso Lopes <bruno.cardoso at gmail.com> wrote: From: Bruno Cardoso Lopes <bruno.cardoso at gmail.com>

For compile and link Basicmath files (using shell script): llvm-gcc -emit-llvm basicmath_small.c -c -o basicmath_small.bc llvm-gcc -emit-llvm cubic.c -c -o cubic.bc llvm-gcc -emit-llvm isqrt.c -c -o isqrt.bc llvm-gcc -emit-llvm rad2deg.c -c -o rad2deg.bc llvm-link basicmath_small.bc cubic.bc isqrt.bc rad2deg.bc -o basicmath.bc

The address qualifier is stored in the type of %result. From that operand, you can get the Value and then call getType. The type for result should be a PointerType which you cast to a PointerType and get the getAddressSpace e.g. cast<PointerType>(Ty)->getAddressSpace() -- Mon Ping On Sep 17, 2008, at 1:06 PM, Villmow, Micah wrote: > How do I access the address qualifier

Kalle: Your patch is similar to what I'd coded (and am testing, which means a couple of hours before I consider committing). Other than cosmetic changes and changing 'NULL' to '0' (it's an integer list, after all). This patch now causes new problems in the CellSPU backend (more stqd's and lqd's), so I have to investigate those before committing the patch.

*1. I have searched the access/setting of LLVMCC_EMITIR_FLAG in the build directory, recursively, and all the output is what I pasted in last email (just the same to the that in source directory). Maybe the configure failed to do it. My command list for building the test suit is as followings:* *(1) cd ~/SRC_DIR/llvm/projects* *(2) svn co http://llvm.org/svn/llvm-project/test-suite/trunk

Scott, In case you missed it, I reimplemented your BuildVectorSDNode::isConstantSplat method following the suggestions from Chris. The revised version passes "make check" for llvm. Assuming that it also passes Evan's tests, I think it should also do what you need for CellSPU. On Feb 25, 2009, at 12:16 PM, Scott Michel wrote: > Evan: > > I work on reverting it,