similar to: [LLVMdev] LLVM position with MIPS, Sunnyvale, CA

1. Senior Compiler Engineer, Stream Compute Team - AMD, Sunnyvale, California We are currently looking for a senior software engineer to join the core team developing our OpenCL compiler stack for multi-core CPU and many-core graphics systems. The selected candidate will be involved in all aspects feature development and maintenance, and will participate in performance tuning for new multi-core

Hi My name is Mark Chen and I'm with Triple Crown Consulting. My company is currently looking for a software engineer with LLVM development experience. Job description is below. Please contact me if anyone is interested in this job opportunity. This position is in the Hardware Accelerator Synthesis software team participating in development of a custom C to RTL synthesis

To all: We have an opening for a recent graduate to work as a Statistical Programmer at Advanced Micro Devices (AMD) in Sunnyvale CA beginning January 2007. AMD is a global supplier of microprocessors and silicon-based solutions to the communications and computer industries. This position will support the development of statistical applications for engineering groups within AMD's technology

My most recent search of FreeBSD-related positions at my employer (Juniper Networks in Sunnnyvale, California) turned up 19 hits: * 17 engineers * 2 IT * I Internships There were some others in other locations (e.g., Bangalore). Please see <https://careers.juniper.net/careers/careers.html> for additional details. Peac, david -- David H. Wolfskill david@catwhisker.org I submit that

NOTE: The position is within the IT organization at Juniper, of which I am not a part. I do not have first-hand knowledge of the working conditions, and cannot speak to that with authority. I would, however, encourage anyone intending to express interest to ask about anything that might be a concern -- preferably during the interview process. My bias would be to favor someone who wishes to

It seems that LLVM is converting all the 16 bit ints into 32 bit ints. Is there a way I can tell LLVM that 16 bit ints are valid and legal and not to do any conversions on them? Thanks, Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. S1-609 One AMD Place Sunnyvale, CA. 94085 P: 408-749-3966 -------------- next part

Hi Folks, At AMD we are growing our ROCm ( https://rocm.github.io/index.html) compiler team. The compiler is built on the llvm compiler foundation, and it supports OpenCL, HCC C++ and HIP for application portability. We are considering all qualified applicants regardless of the experience level. Requirements are: Strong background in compilers. Strong C/C++ programming skills.

How do I match against this instruction? 01ABDA58: i64,ch = load 01ABD948, 01ABD8C0, 01AB1350 <null:0> This is the first time I've seen NULL in the memory operand location. Any idea on how this could be mapped with tablegen correctly? Thanks, Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. S1-609 One AMD Place Sunnyvale,

I'm hitting an issue where legalizeOp is overflowing the stack. Are there any recommended ways of getting around this? The bitcode that causes this issue is attached. Thanks, Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. S1-609 One AMD Place Sunnyvale, CA. 94085 P: 408-749-3966 -------------- next part -------------- An

What is the difference between these two functions? The header file for TargetLowering class says that LowerArguments must be implemented, but only the Sparc and IA64 backends implement them. X86, PowerPC and CellSPU implement LowerFORMAL_ARGUMENTS, but I can find a setOperationAction that states that they should be lowered. Can someone please explain this for me? Thanks, Micah Villmow

Are you marking i16 a legal type? In XXISelLowering.cpp, you should assign it a register class. e.g. addRegisterClass(MVT::i16, XX::i16RegisterClass) Evan On Feb 2, 2009, at 12:19 PM, Villmow, Micah wrote: > It seems that LLVM is converting all the 16 bit ints into 32 bit > ints. Is there a way I can tell LLVM that 16 bit ints are valid and > legal and not to do any conversions

Currently with my understanding of using callingconv.td I still need to lower three functions, FORMAL_ARGUMENTS, CALL, and RET. Is there any known way to have LLVM automagically generate code from tablegen without having to custom lower these functions? The reasoning for this is that all registers are virtual in my backend and I have specified for llvm to use it's generic dynamic stack

It depends on how your target models its addressing mode. Targets with complex addressing modes usually isel addresses with custom code. Evan On Mar 6, 2009, at 4:05 PM, Villmow, Micah wrote: > How do I match against this instruction? > 01ABDA58: i64,ch = load 01ABD948, 01ABD8C0, 01AB1350 <null:0> > > > This is the first time I’ve seen NULL in the memory operand >

Are you running with restricted stack size, e.g. in a pthread process? Evan On Mar 10, 2009, at 5:16 PM, Villmow, Micah wrote: > I’m hitting an issue where legalizeOp is overflowing the stack. Are > there any recommended ways of getting around this? > > The bitcode that causes this issue is attached. > > Thanks, > Micah Villmow > Systems Engineer > Advanced

I have a pass that modifies my machine dependent instructions and I have ran into a situation where I want to remove all instructions that an instruction is dependent on when I remove an instruction. Is there a way to do this using the API calls? For example, I have a sequence of instructions a = b + c d = c * c store d, *a load e, *a f = e + d since the store and load are

I am running into an issue where if I have multiple functions compiled in the same compilation unit the stack offset is not starting at zero. For example: func1(...) { ... } func2(...) { ... } Say the first function uses 64 bytes of the stack and an assumed offset of 0 and the second function uses 32 bytes of the stack but an assumed offset of 64. I've found out how to get the

I need to support 16 bit floats for some operations, outside of datatypes.td and the constants class, is there anything else I will need to modify to add f16 support? Thanks, Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. S1-609 One AMD Place Sunnyvale, CA. 94085 P: 408-749-3966 -------------- next part -------------- An HTML

I've patched valuetypes.td/h to add data types that my backend needs to support. There seems to be a lot of assumptions made in other spots of the code that limit the number of data types to 32. I need to add a few more types, but once I go over this limit llvm starts acting wonky. I found all the items that are hard coded to 32 and a section that isn't, but I cannot figure out how to

Hi, I'm trying to compile the benchmarks from Mibench suite with the application of the all LLVM's tranformation passes. Moreover, I'm trying to generate assembly code for Mips architecture for extraction of energy and performance metrics. For this, for example, initially I compile the sources and link them generating a bitecode file. After, I apply each optimization using opt tool:

it appears that by default some Apple configuration is assumed, since a simple make complains GNUmakefile:16: /CoreOS/Standard/Standard.make: No such file or directory We started with a subversion checkout, in case it matters. --------------------------------------------------------------------+ Thomas Plum, Plum Hall Inc, 3 Waihona Box 44610, Kamuela HI 96743 USA tplum at plumhall.com