similar to: [LLVMdev] Reporting errors in inline assembly

On Fri, Jul 1, 2011 at 4:09 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > I want to report a problem with an inline assembly instruction from a code generator pass? > > How can I do that with the proper diagnostic format and source location? > > Right now we only get: > > clang -c /d/g/clang-tests/gcc-4_2-testsuite/src/gcc.target/i386/pr30848.c > fatal

I want to report a problem with an inline assembly instruction from a code generator pass? How can I do that with the proper diagnostic format and source location? Right now we only get: clang -c /d/g/clang-tests/gcc-4_2-testsuite/src/gcc.target/i386/pr30848.c fatal error: error in backend: Inline asm output regs must be last on the x87 stack But gcc-4-2 can: $ gcc-4.2 -c

On Jul 1, 2011, at 4:08 PM, Jakob Stoklund Olesen wrote: > I want to report a problem with an inline assembly instruction from a code generator pass? > > How can I do that with the proper diagnostic format and source location? > > Right now we only get: > > clang -c /d/g/clang-tests/gcc-4_2-testsuite/src/gcc.target/i386/pr30848.c > fatal error: error in backend: Inline

On 12 May 2016 at 16:19, Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: > The problem in PR24071 seemed to be that clang proceeded with compilation > even though the inline asm was not valid. I'm not sure that there is value > in trying to make the backend continue compiling code that most likely has > no meaning. I'm not 100% convinced that is the

I'm getting this error in RegAllocFast.cpp in compiling one source file in test-suite as the result of a new Mips fast-isel patch I was testing. It apparently just generates bad code and continues? // Nothing we can do. Report an error and keep going with a bad allocation. if (MI->isInlineAsm()) MI->emitError("inline assembly requires more registers than

On Sun, 03 Jun 2012 12:12:06 -0700 Chris Lattner <clattner at apple.com> wrote: > > On Jun 2, 2012, at 11:01 AM, Mikael Lyngvig wrote: > > > If I may add my two cents: > > > > I am planning to use LLVM as the backend for a compiler I am > > working on. And I wholeheartedly agree with Justin that it is a > > problem, if LLVM is allowed to freely

It seems like it might be a legitimate complaint from the register allocator. It's trying to get an accumulator (not a general purpose register) and the accumulator is 64 bit. It's using a part of the Mips backend that I have not worked in so I have to research this a bit. The multiply instruction is a pseudo multiply in the mips backend and it needs the accumulator which a special

On Sun, Jun 3, 2012 at 7:12 PM, Justin Holewinski <justin.holewinski at gmail.com> wrote: > On Sun, Jun 3, 2012 at 4:15 PM, Hal Finkel <hfinkel at anl.gov> wrote: >> >> On Sun, 03 Jun 2012 12:12:06 -0700 >> Chris Lattner <clattner at apple.com> wrote: >> >> > >> > On Jun 2, 2012, at 11:01 AM, Mikael Lyngvig wrote: >> >

Dear all, I am looking to output assembly comments in my emitPrologue() function, just for my own readability. Searching for a way to do this found me this thread - http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-October/043722.html, which says that the best way to output comments from somewhere like emitPrologue() is to: 1. Create an MDString for the comment. 2. Attach it to an LLVM

On Sun, Jun 3, 2012 at 4:15 PM, Hal Finkel <hfinkel at anl.gov> wrote: > On Sun, 03 Jun 2012 12:12:06 -0700 > Chris Lattner <clattner at apple.com> wrote: > > > > > On Jun 2, 2012, at 11:01 AM, Mikael Lyngvig wrote: > > > > > If I may add my two cents: > > > > > > I am planning to use LLVM as the backend for a compiler I am >

So, an update. I have managed to generate comments, although it does create a non-existent instruction. My method is as follows (and I would appreciate any comments on how to do it "better", although note that this won't make it into the final code :).) 1. I declared a "fake" instruction type to hold comments, ala: class FakeInst<dag outs, dag ins, string asmstr,

On Fri, Jan 29, 2016 at 10:22 AM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 1/28/2016 8:11 PM, Rail Shafigulin via llvm-dev wrote: > >> >> Would anyone be able to figure out why this is happening? I can provide >> more code if needed. >> > > The error message should show what types have been inferred so far. > > You

On Mon, Jun 4, 2012 at 11:46 AM, Eli Friedman <eli.friedman at gmail.com>wrote: > On Sun, Jun 3, 2012 at 7:12 PM, Justin Holewinski > <justin.holewinski at gmail.com> wrote: > > On Sun, Jun 3, 2012 at 4:15 PM, Hal Finkel <hfinkel at anl.gov> wrote: > >> > >> On Sun, 03 Jun 2012 12:12:06 -0700 > >> Chris Lattner <clattner at apple.com>

I've run the tests from clang-tests/trunk/gcc-4_2-testsuite on a Ubuntu x86-64 Linux box with the following results: === gcc Summary === # of expected passes 29946 # of unexpected failures 9938 # of unexpected successes 29 # of expected failures 28 # of unresolved testcases 1451 # of untested testcases 273 # of unsupported tests 811 pid is 4456

Hi John, On Wed, Sep 22, 2010 at 11:32 AM, John Thompson <john.thompson.jtsoftware at gmail.com> wrote: > I've run the tests from clang-tests/trunk/gcc-4_2-testsuite on a Ubuntu > x86-64 Linux box with the following results: > >         === gcc Summary === > > # of expected passes        29946 > # of unexpected failures    9938 > # of unexpected successes    29

Not sure what you mean. I.OutOperandList == (outs CPU16Regs:$rx) I.InOperandList == (ins CPU16Regs:$ry, CPU16Regs:$rz) On 07/02/2012 09:26 PM, Sean Silva wrote: > I think you're missing the template args for `FRRR16_ins` in the first > argument. The switch in TGParser::ParseType() doesn't cover the case > of types with template args though... which makes me wonder what is

Hi All, Is it possible to initialize(set up) register attributes when we define an instruction? like if a register is defined like this: " class SC_Register<bits<8> register_num, REG_FLAG SC_X, REG_FLAG SC_Y, REG_FLAG SC_Z, REG_FLAG SC_W, string asmstr> : Register<asmstr> { let HWEncoding{7-0} =

llvm/lib/Target/X86/X86InstrInfo.td: class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr> : Instruction { .... dag OperandList = ops; string AsmString = AsmStr; } def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), "mov{l} {$src, $dst|$dst, $src}">; I cannot find any document on initializing the

I'm starting to look into binary instruction encodings in TableGen, and I'm a bit confused on how the instruction fields are populated. Perhaps I'm just being dense, but I cannot see how SDAG operands are translated into the encoding fields. Can someone please explain the following snippet from the PPC back-end. The AND instruction in PPC is defined as: 1011 def AND :

I am trying to make some modifications to our code generator that will produce better code, but require adding new patterns. What I am trying to do is take a register/register pattern and change it to a register/immediate. So for example, I have this pattern: class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { let Namespace =